Senior RTL Verification Lead – SoC (Remote)

TechTeamz; A distancia; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

A tech company is seeking a skilled Digital Verification Engineer to oversee the development and validation of next-generation SoC designs. This role focuses on functional verification at the RTL level, ensuring correctness across high-speed and low-speed interfaces. Responsibilities include developing verification plans and collaborating with design teams. The position offers permanent employment with full remote working conditions available anywhere in Spain. Ideal candidates should have a strong background in RTL-level verification and hands-on experience with SystemVerilog and UVM.

Formación

• Solid background in Front-End (RTL-level) Functional Verification.
• Hands-on experience with SystemVerilog, UVM, assertions (SVA), and coverage-driven verification.
• Strong knowledge of high-speed and low-speed interface protocols.

Responsabilidades

• Develop and execute functional verification plans for complex SoC subsystems.
• Oversee verification activities throughout the development lifecycle.
• Create and maintain verification environments, testbenches, and test cases.

Conocimientos

Front-End (RTL-level) Functional Verification

SystemVerilog

UVM

Assertions (SVA)

Coverage-driven verification

Protocol verification IP (VIP)

Debugging complex design/verification issues

High-speed interface protocols

Low-speed interface protocols

Descripción del empleo

A tech company is seeking a skilled Digital Verification Engineer to oversee the development and validation of next-generation SoC designs. This role focuses on functional verification at the RTL level, ensuring correctness across high-speed and low-speed interfaces. Responsibilities include developing verification plans and collaborating with design teams. The position offers permanent employment with full remote working conditions available anywhere in Spain. Ideal candidates should have a strong background in RTL-level verification and hands-on experience with SystemVerilog and UVM.