Senior Digital IC Verification Engineer - RISC-V

ic resources; Madrid; Presencial; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

A leading semiconductor recruitment agency is seeking a digital verification engineer to work on cutting-edge RISC-V technology in Madrid. The ideal candidate will have 5+ years of experience, a Masters or PhD in Electronics, and expertise in UVM environments, ASIC design, and System Verilog. Responsibilities include contributing to advanced technology nodes and managing ASIC verification environments. Visa sponsorship may be available depending on qualifications.

Formación

• 5+ years of experience in digital verification engineering.
• Experience with ASIC / FPGA design and verification.
• Strong understanding of digital ICs / ASIC IP.

Responsabilidades

• Contribute to the development of advanced technology nodes.
• Set up and manage ASIC verification environment.
• Develop digital test plans and create test benches.

Conocimientos

UVM environments

ASIC/FPGA development

System Verilog

Scripting / coding skills (C/C++, Python)

Verification Metrics definition

Educación

Masters or PhD in Electronics / Microelectronics

Herramientas

vManager

vPlan

Descripción del empleo

Overview

Exciting opportunity to work on the latest cutting edge RISC‑V technology in the semiconductor industry. In this new role as digital verification engineer you will contribute to advanced technology nodes, consisting of RISC‑V designs, ARM & CPU architecture, PCIe protocols and machine learning.

Responsibilities

I am looking to speak with digital verification engineers with 5+ years of experience who have the following skills:

• Masters or PhD degree in Electronics / Microelectronics or similar field
• 5+ years' experience in UVM environments & process
• ASIC / FPGA development
• System Verilog for IP / SOC Verification of digital ICs / ASIC IP or chips
• Complex ASIC designs & architecture for advanced technology nodes
• Verification Metrics definition, Coverage analysis and debugging skills.
• Knowledge and experience on setting up an ASIC Verification environment, methodology and flow.
• vManager, vPlan and Regressions, etc.
• Digital Test Plan definition / creating / set‑up test benches
• Scripting / coding skills - C/C++, python etc.

Bonus Skills

• RISC‑V / CPU / GPU (this is a bonus, not required)
• Knowledge of SOC verification is also a bonus

Sponsorship

***Visa sponsorship can be offered if required (dependent on experience/qualifications)***

Verification Engineer • Madrid, Community of Madrid