SoC Design Engineer

Theconstructsim; Vaughan; On-site; CAD 120,000 - 150,000; Full time

Job summary

A leading tech firm in Canada is seeking a SoC Design Engineer to develop and execute timing constraints for high-performance designs. The role requires over 10 years of ASIC implementation experience, with expertise in STA constraints and EDA tools such as Synopsys. Candidates should have strong analytical and communication skills to work effectively across teams. The position offers a competitive salary ranging from $120,000 to $150,000 annually.

Qualifications

• 10+ years of experience in ASIC implementation and CAD methodology.
• Experience with multi-voltage design and timing closure.
• Hands-on experience with physical design implementation is a plus.

Responsibilities

• Develop timing constraints for SoC designs.
• Own timing flow to meet SoC requirements.
• Engage with design teams for requirement understanding.
• Work with physical implementation teams to debug timing failures.

Skills

ASIC implementation experience

Timing analysis

STA constraints generation

EDA tools expertise

Scripting languages (TCL, Perl, Python)

Analytical skills

Strong communication skills

Tools

Synopsys DC

Primetime

Job description

Job Title: SoC Design Engineer

Location: Thornhill, ON, Canada

KEY RESPONSIBILITIES

• Develop block and SoC timing constraints, full chip STA setup and signoff of multi‑corner multi‑voltage designs.
• Own the timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management.
• Engage closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges.
• Engage closely with physical implementation teams to ensure designs meet QoR and debug timing failures.

PREFERRED EXPERIENCE

• 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high‑performance designs.
• Demonstrated ability in ASIC STA constraints generation, timing analysis, timing convergence and ECOs at both block and full‑chip level.
• Implementation experience and knowledge handling multi‑voltage design; STA closure of low power and multi‑power mode designs is an added advantage.
• Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime.
• Proficiency in scripting languages such as TCL, Perl and/or Python.
• Experience developing scripts to automate design flow and analysis.
• Hands‑on experience with Physical Design implementation is a plus.
• Strong communication skills, ability to multi‑task across projects, and work with geographically spread‑out teams.
• Strong analytical/problem‑solving skills and pronounced attention to detail.

Compensation: $120,000.00 - $150,000.00 per year

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