RTL Design Engineer

Capgemini Engineering; Markham; On-site; CAD 90,000 - 120,000; Full time

Job summary

A global tech consulting firm in York Region, Markham, is seeking a Mid-Senior RTL Design Engineer to join their collaborative team. This role involves designing synthesizable RTL for SoC components and optimizing performance, power, and quality. The ideal candidate has at least 5 years of experience in RTL design and proficiency with ASIC tools. Competitive full-time position with opportunities for innovation and collaboration across global sites.

Qualifications

• 5+ years of hands-on RTL design experience targeting advanced ASIC technologies.
• Proficiency with ASIC design tools including lint, CDC, LEC, and gate-level simulations.
• Strong scripting skills for automation and efficiency.

Responsibilities

• Design and maintain RTL for SoC and subsystem components.
• Collaborate with architecture, design, and verification teams.
• Support synthesis, timing closure, and power optimization efforts.

Skills

RTL design experience

Verilog / SystemVerilog

ASIC design tools (Synopsys, Cadence)

Scripting (Python, Perl, TCL, Bash)

SoC integration and networking standards

Education

Bachelor’s or Master’s degree in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Job description

Overview

Direct message the job poster from Capgemini Engineering

Join a collaborative and innovative team as an RTL Design Engineer, where you'll contribute to cutting-edge ASIC development in a dynamic, multi-disciplinary environment. In this role, you’ll design and maintain synthesizable RTL for SoC and subsystem components, working closely with architecture, verification, and physical design teams across global sites. You’ll help ensure performance, power, and quality goals are met through simulation, debugging, and integration support, while contributing to technical discussions and emulation efforts.

Your role

• Design and maintain RTL for SoC and subsystem components using Verilog / SystemVerilog
• Collaborate with architecture, design, and verification teams across multiple time zones
• Support synthesis, timing closure, and power optimization efforts
• Debug simulation failures and assist in post-silicon validation
• Contribute to emulation activities and technical status meetings

Your skills and experience

• Bachelor’s or Master’s degree in Electrical or Computer Engineering, with 5+ years of hands-on RTL design experience targeting advanced ASIC technologies.
• Proficiency with ASIC design tools (Synopsys, Cadence), including lint, CDC, LEC, and gate-level simulations.
• Strong scripting skills (Python, Perl, TCL, Bash) for automation and efficiency.
• Solid understanding of SoC integration, bus protocols (AXI, AHB, AMBA), and networking / encryption standards.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering and Consulting

Industries

• IT Services and IT Consulting and Business Consulting and Services

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