Senior Principal DFT Engineer

Broadcom; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading technology company in Singapore is seeking a Senior Design-for-Test (DFT) Engineer to join its SoC / ASIC development team. The successful candidate will implement and verify DFT solutions, ensuring optimal test coverage. Responsibilities include developing DFT architectures, performing verification and collaborating with cross-functional teams. A Bachelor's or Master's degree in a related field is required, along with a minimum of 3 years of DFT design experience. The role demands strong understanding of test architectures and hands-on experience with DFT tools.

Qualifications

• Minimum 3 years of experience in DFT design and verification.
• Strong understanding of scan-based test architectures.
• Hands-on experience with DFT tools such as Siemens Tessent.

Responsibilities

• Develop and implement DFT architectures for hierarchical designs.
• Perform scan insertion and test compression.
• Validate SSN topology managing scan chain and clock domains.

Skills

DFT design and verification

Scan-based test architectures

Scripting skills in TCL, Perl or Python

Education

Bachelors or Masters in Electrical/Computer Engineering

Tools

Siemens Tessent

Advantest

Teradyne

Job description

Position of Senior DFT Engineer

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC / ASIC DFT development team.

The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs.

This position involves hands‑on work in DFT insertion and comprehensive DFT verification to ensure first‑pass silicon success.

You will collaborate closely with Physical design team ATE test teams to develop efficient high‑quality test strategies aligned with industry standards.

Key Responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs including both block‑level and top‑level DFT integration.
• Perform scan insertion test point insertion and test compression using SSN or equivalent compression architectures.
• Validate Serial Stream Network (SSN) topology managing scan chain balancing clock domain crossings.
• Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip‑level testability.
• Generate and analyze ATPG patterns for stuck‑at transition and path delay faults to ensure optimal test coverage.
• Perform DFT verification including verilog / gate level simulation.
• Work closely with cross‑functional teams to resolve DFT / testing timing challenges.
• Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL / WGL) for tester compatibility and production readiness.
• Support silicon bring‑up production test debugging through Diagnostics and failure analysis.

Qualifications

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering or related field.
• Minimum 3 years of experience in DFT design and verification (5 years preferred for senior roles).
• Strong understanding of scan‑based test architectures, test compression and hierarchical DFT implementation.
• Hands‑on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis and gate‑level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl or Python for DFT automation.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race color creed religion sex sexual orientation national origin citizenship disability status medical condition pregnancy protected veteran status or any other characteristic protected by federal state or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA please be sure to fill out a home address as this will be used for future correspondence.