Senior AMS Verification Engineer

ic resources; Trento; In loco; EUR 40.000 - 60.000; Tempo pieno

Descrizione del lavoro

A global organization in Italy is seeking an AMS Verification Engineer. The role involves verifying the functionality and performance of Analog and Mixed-Signal designs. Key responsibilities include developing verification plans, executing tests, and collaborating with design engineers. Candidates must have proven IC verification experience and familiarity with tools such as Cadence and Synopsys. This position offers an exciting opportunity to contribute to innovative design work.

Competenze

• Proven IC verification experience required.
• Strong understanding of tools necessary.

Mansioni

• Developing verification plans for AMS designs.
• Implementing and executing verification tests.
• Collaborating with design engineers to identify and resolve design issues.
• Performing functional and performance verification of analog and mixed-signal circuits.
• Developing and maintaining verification infrastructure and automation scripts.
• Analysing and debugging simulation failures.
• Documenting verification procedures, results, and findings.
• Participating in periodic reporting, design reviews, internal seminars, and training sessions.

Conoscenze

IC verification experience

Collaboration with design engineers

Analysing and debugging

Strumenti

Cadence

Synopsys

Descrizione del lavoro

I am seeking an AMS Verification Engineer to join a global organisation based in Italy. You will have the chance to contribute to verifying the functionality and performance of Analog and Mixed-Signal designs.

Key responsibilities will include, but are not limited to :

• Developing verification plans for AMS designs.
• Implementing and executing verification tests.
• Collaborating with design engineers to identify and resolve design issues.
• Performing functional and performance verification of analog and mixed-signal circuits.
• Developing and maintaining verification infrastructure and automation scripts.
• Analysing and debugging simulation failures.
• Documenting verification procedures, results, and findings.
• Participating in periodic reporting, design reviews, internal seminars, and training sessions.

To be considered for this role, you must possess proven IC verification experience and a strong understanding of tools such as Cadence oropsys.

For further information, please contact Parm Shergill.