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Formal Verification Engineer - Semiconductors
Job summary
A high-tech company in the UK is looking for a Formal Verification Engineer with extensive experience in verifying FPGA or ASIC designs within the semiconductor industry. Responsibilities include developing methodologies, participating in RTL design reviews, and preparing verification plans. Candidates should have strong scripting skills, in-depth knowledge of formal verification techniques, and a Bachelor's or Master's degree in Electronics. A competitive salary package and hybrid working options are available.
Qualifications
- 5+ years experience in the semiconductor industry.
- Proven experience in the verification of complex designs.
- Strong knowledge of metrics-driven verification and test planning.
Responsibilities
- Develop formal verification methodologies.
- Participate in RTL design reviews.
- Prepare design verification plans and track design bugs.
Skills
Education
Tools
Great opportunity for a Formal Verification Engineer with a proven track record of verifying complex FPGA or ASIC designs within the Semiconductor industry. Youll play a key role in an innovative High-Tech company revolutionizing wired connectivity and pushing the boundaries of AI related innovation. A great salary package will be offered with Hybrid working and career development opportunities.
Skills and experience for the Formal Verification Engineer should include:
- Bachelors / Masters Degree in Electronics related discipline.
- 5+ years experience of working within the semiconductor industry.
- Proven experience in the Verification of complex designs - FPGA or ASIC.
- Good scripting skills (Python, Perl or TCL for automation).
- Working with RTL designers to develop a formal micro-architecture specification.
- In-depth understanding of Formal Verification techniques.
- Strong knowledge on Metrics-driven verification including test planning and coverage closure.
- Proficiency in temporal logic assertion based languages such as SVA or PSL.
Of particular interest is knowledge of Cadence JasperGold and VManager and familiarity with SerDes and high level protocols.
The successful Formal Verification Engineer will take responsibility for developing formal verification methodologies; participating in RTL design reviews, preparing design verification plans as well as tracking and closing design bugs.
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.