Stage Ingénieur Implementation Physique Digitale (FM)

NXP Semiconductors; Grenoble; Sur place; EUR 40 000 - 60 000; Plein temps

Résumé du poste

A technology company is looking for an intern to join their Digital Physical Implementation team for a six-month assignment. The intern will manage the physical implementation flow for sub-systems and conduct static timing analysis. Candidates should have a Master's degree in microelectronics or ASIC design, with knowledge in Verilog, SystemVerilog, Perl, Python, and a good level of English. This role is located in Grenoble, France.

Qualifications

• Master's degree or last year of engineering school in microelectronics or ASIC design.
• Strong knowledge in Verilog and/or SystemVerilog.
• Familiarity with Perl and/or Python, TCL, Unix.
• Good level of English required for international teamwork.

Responsabilités

• Manage physical implementation flow for sub-systems including topographical synthesis and routing.
• Conduct static timing analysis and implement ECO.

Connaissances

Knowledge in Verilog

Knowledge in SystemVerilog

Knowledge in Perl

Knowledge in Python

Knowledge in TCL

Knowledge in Unix

Good level of English

Formation

Master Degree in microelectronics or ASIC design

Description du poste

Context

We are looking for an intern for six months to join the Digital Physical Implementation team in charge of physical implementation of SoC 16nm.

Your responsibilities

• Take charge of physical implementation flow for a sub‑system: topographical synthesis, placement, clock‑tree synthesis, routing, timing closure.
• Static Timing Analysis, ECO implementation, equivalence checking.

Your profile

• Education level: Master Degree / last year of engineering school in microelectronics / ASIC design.
• Knowledge in Verilog and/or SystemVerilog.
• Knowledge in Perl and/or Python, TCL, Unix.
• A good level of English is required working in an international multi‑site team.

More information about NXP in France...

Contexte

Nous recrutons un stagiaire de fin d'étude sur une durée de 6 mois pour rejoindre l'équipe Implémentation Physique Digitale en charge de l'implémentation physique de SoC en 16nm.

Vos missions

• Conduite du flot d'implémentation physique sur les sous‑systèmes : synthèse topographique, placement des standard cells, construction du réseau d'horloge, routage des signaux, analyse de la congestion, convergence, optimisation du timing et de la consommation.
• Vérifications physiques (DRC, LVS, antenne, électromigration, power et signaux).
• Analyse statique des timings, implémentation d'ECO, vérification formelle.

Votre profil

• Niveau d'études : Bac +5 en dernière année d'école d'ingénieur en microélectronique / conception de circuits intégrés.
• Connaissances en langage Verilog et/ou SystemVerilog.
• Connaissances en langages Perl et/ou Python, TCL, Unix.
• Un bon niveau d'anglais est exigé.