Senior Analog PLL Architect & Technical Lead

ic resources; Paris; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

A leading semiconductor company in Paris is seeking a dynamic Analog Designer for the role of PLL Analog IC Technical Lead. The ideal candidate will have 10+ years of experience in chip-level architecture and design, with a strong background in low jitter PLL design and mixed-signal IC projects. This role involves leading the analog design work, collaborating with technical teams, and contributing to the complete design flow. Strong knowledge of Cadence tools is required, and fluency in English is necessary.

Qualifications

• 10+ years of hands-on experience in chip-level and circuit-level architecture definition, transistor level design and verification.
• Experience in PLL design in advanced node CMOS / FDSOI technologies (22nm and beyond).
• Strong experience in mixed-signal IC project and technical leader role.

Responsabilités

• Define the architecture and design of high performance RF PLL.
• Lead and support analog design work from transistor schematic to GDSII.
• Collaborate with other technical leaders to define IC architecture.

Connaissances

Analog design

Low jitter LC based PLL design

Mixed-signal IC design

Analytical and problem-solving skills

Team collaboration

Formation

MSc or PhD in Electrical Engineering

Outils

Cadence Spectre

Cadence design flow

EM tools

Description du poste

A leading semiconductor company in Paris is seeking a dynamic Analog Designer for the role of PLL Analog IC Technical Lead. The ideal candidate will have 10+ years of experience in chip-level architecture and design, with a strong background in low jitter PLL design and mixed-signal IC projects. This role involves leading the analog design work, collaborating with technical teams, and contributing to the complete design flow. Strong knowledge of Cadence tools is required, and fluency in English is necessary.