Digital IC Backend Design Engineer

Arago Inc.; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Competitive cash compensation

Meaningful stock option plan

Relocation bonus

Healthcare coverage

25 days of PTO

25 days PTO

Résumé du poste

A forward-thinking AI company in Paris is looking for a Digital Backend Design Engineer to implement digital designs from RTL to GDSII. The candidate should have a Master's or PhD in Electrical Engineering and at least 4 years of experience. Proficiency in Cadence tools and Tcl scripting is essential. The role offers competitive pay, stock options, and a dynamic multicultural environment with opportunities for growth.

Qualifications

• 4+ years experience in digital IC backend implementation.
• Experience with advanced technology nodes (22nm or below preferred).
• Solid grasp of static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
• Strong understanding of Place & Route (P&R), STA, DRC/LVS, IR drop, EM analysis.
• Experience with technology nodes (22nm or below).
• Skilled in Tcl scripting for backend automation.
• Experience in hierarchical or full‑chip implementation is preferred.

Responsabilités

• Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and verification.
• Develop and optimize digital backend flows.
• Support tapeout preparation and final signoff processes.
• Collaborate with front‑end designers to address timing and interface issues.
• Support tapeout preparation and final signoff processes.

Connaissances

Backend EDA tools proficiency

Tcl scripting for automation

Strong understanding of P&R

Experience in hierarchical or full-chip implementation

IR drop

EM analysis

Tcl scripting

Hierarchical design

Full‑chip implementation

Formation

Master’s or PhD in Electrical/Electronic Engineering

Outils

Cadence Innovus

Cadence Genus

Description du poste

Meet Arago and the Aragonians

Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles:

1. Do great things: we deliver work we’re proud to sign our name to.

2. High velocity: speed matters. We move quickly, one step at a time.

3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.

What you’ll do

As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting‑edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.

Required Skills and Experience

• Master’s or PhD degree in Electrical/Electronic Engineering or a related field.

• 4+ years experience in digital IC backend implementation.

• Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.

• Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.

• Experience with advanced technology nodes (22nm or below preferred).

• Skilled in Tcl scripting for automation of backend flows.

• Experience in hierarchical or full‑chip implementation is preferred.

Responsibilities

• Execute full‑chip and block‑level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.

• Develop and optimize the digital backend flow.

• Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).

• Collaborate with front‑end designers to address timing and logical/physical interface issues.

• Support tapeout preparation and final signoff processes.

Pay and benefits

• Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.

• Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full‑time offers).

• Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.

• Healthcare coverage (including family‑friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.

• Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.

• A high‑paced, multicultural (with 9 nationalities), and engineering‑led environment.