Physical Design Engineer (DSP)

Qualcomm; Markham; On-site; CAD 85,000 - 120,000; Full time

Job summary

A leading semiconductor company in Canada is seeking a talented Physical Design Engineer to innovate and implement DSP cores. You will handle complete physical design flows, optimize power and performance, and ensure tapeout readiness. Ideal candidates should hold a Bachelor's or Master's in Electrical Engineering, with over 7 years of experience and expertise in relevant tools like Cadence Innovus and Synopsys. This role offers a collaborative environment focused on innovation and technical excellence.

Benefits

Cutting-edge projects

Collaborative team environment

Qualifications

• 7+ years of industry experience in Physical Design for ASIC/SoC.
• Hands-on expertise with timing closure tools.
• Strong understanding of DFT and ECO flows.

Responsibilities

• Own and execute complete Physical Design flow from netlist to GDSII.
• Perform PPA analysis and optimization.
• Manage tapeout activities and ensure DRC, LVS sign-off.

Skills

Physical Design flow expertise

PPA optimization

Scripting (Perl/TCL, Python)

Timing optimization

Power integrity analysis

Place & Route tools

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

Synopsys PrimeTime

Job description

Company: Qualcomm Canada ULC

Job Area: Engineering Group, Engineering Group > ASICS Engineering

General Summary

QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state‑of‑the‑art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes.

Key Responsibilities

• Own and execute complete Physical Design flow from netlist to GDSII, including:
• Floorplanning, power planning, IR‑drop analysis
• Placement, MMMC clock tree synthesis, routing
• Timing optimization and closure across multiple modes and corners
• Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
• Develop and enable low‑power implementation methods and customized P&R strategies for area reduction and performance improvement.
• Debug timing violations, implement timing fixes, and roll in functional ECOs.
• Conduct RC extraction, signal integrity, crosstalk noise/delay analysis, and formal verification.
• Manage tapeout activities, ensuring sign‑off for DRC, LVS, timing, power integrity, and reliability.
• Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
• Contribute to flow enhancements and automation using scripting (Perl/TCL, Python, Linux shell).

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of industry experience in Physical Design for ASIC/SoC.
• Proven tapeout experience with successful delivery of complex cores.
• Hands‑on expertise with:
  • Place & Route tools: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler
  • Timing closure: Synopsys PrimeTime
  • Physical verification: DRC/LVS sign‑off flows
• Strong understanding of DFT, multi‑mode/multi‑corner designs, and ECO flows.
• Proficiency in scripting languages (Perl, TCL, Python) and Linux/Unix environments.

Preferred Skills

• Experience with latest advanced technology nodes.
• Knowledge of power integrity analysis (IR‑drop, EM) and low‑power design techniques.
• Familiarity with formal verification, understanding of DFM and post‑silicon validation.
• Ability to work in a fast‑paced environment and communicate effectively with cross‑functional teams.

Why Join Us?

• Work on cutting‑edge DSP cores for next‑generation products.
• Opportunity to lead tapeout and PPA optimization for high‑performance, low‑power designs.
• Collaborative team environment with strong focus on innovation and technical excellence.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Applicants

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail [e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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