Analog Ic Design Lead

Whatjobs; Pisa; In loco; EUR 70.000 - 90.000; Tempo pieno

Descrizione del lavoro

A growing technology company in Italy seeks a Senior Analog IC Design Engineering Lead to innovate in high-speed PLL and power management designs. The successful candidate will work on cutting-edge technologies in a collaborative environment. This role requires a strong background in CMOS design and experience with tools like Cadence and Spectre. Excellent problem-solving skills are essential.

Competenze

• Proven track record in PLL and power management design, ideally at or near 12nm nodes.
• Strong background in CMOS analog design fundamentals.
• Detail oriented with excellent problem solving skills.

Mansioni

• Design and develop high-speed PLLs (10 GHz and above).
• Implement on-chip power management circuits such as LDOs and DACs.
• Collaborate closely with digital, systems and photonic teams on complex mixed signal integration.
• Run simulations, oversee layout and verify performance of analog building blocks.
• Bring industry trends and design innovations into the development cycle.

Conoscenze

High-speed PLL design

Power management design

CMOS analog design

Problem solving

Strumenti

Cadence

Spectre

Descrizione del lavoro

I am recruiting for a Senior Analog IC Design Engineering Lead on behalf of my client, a growing technology company developing next-generation solutions for high-performance data communication. The position is focused on high-speed Phase Locked Loop design and integrated power management within advanced CMOS nodes.

The Senior Analog IC Design Engineering Lead will contribute to cutting-edge developments in energy-efficient interconnects.

Key responsibilities

• Design and develop high-speed PLLs (10 GHz and above)
• Implement on-chip power management circuits such as LDOs and DACs
• Collaborate closely with digital, systems and photonic teams on complex mixed signal integration
• Run simulations, oversee layout and verify performance of analog building blocks
• Bring industry trends and design innovations into the development cycle

Required experience

• Proven track record in PLL and power management design, ideally at or near 12nm nodes
• Strong background in CMOS analog design fundamentals
• Proficient with tools like Cadence and Spectre
• Detail oriented with excellent problem solving skills

To be considered for this opportunity, you will need to have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment.