Silicon Validation Engineer Intern

Arm; Valbonne; Hybride; EUR 60 000 - 80 000; Plein temps

Résumé du poste

A prominent technology firm in Valbonne is seeking an intern for its Silicon Validation team. The role involves analyzing tools, developing a Python tool, and prototyping with FPGA. The ideal candidate should be pursuing a Master's degree in relevant fields and have skills in C++ and Python. Competitive salary and learning opportunities are offered.

Prestations

Competitive salary

Mentoring and development opportunities

Social activities and networking

Qualifications

• Currently enrolled in a relevant Masters Degree.
• Demonstrate autonomy and willingness to learn new concepts.
• Familiar with FPGA development.

Responsabilités

• Analyzing existing tools for state-of-the-art design concepts.
• Learning DFT and iJTAG concepts.
• Developing a Python tool to perform iJTAG operation.

Connaissances

C++ proficiency

Autonomy

Proficiency in Python

Familiarity with FPGA development

Formation

Masters Degree in Electronics, Embedded systems or Microelectronics

Description du poste

Overview

Arm is hiring an intern for its Silicon Validation team. The team focuses on validating and characterizing Arm IPs using the latest generation of silicon nodes. The DFT team supplies files describing the on-chip iJTAG (IEEE P1687) network. Major EDA tools use these files to generate static test patterns for specific IPs, which are then run on ATE. We’d like to try an alternative workflow that’s better suited to bench work: performing dynamic iJTAG reads and writes targeting the IP under test. We plan to evaluate MAST — a tool originating from prior academic research — and, if successful, apply it to our current test chips; if the evaluation is inconclusive, we’ll develop a similar tool with an improved approach. In either case, we will also need documentation, Python bindings, and an FPGA implementation of iJTAG for testing purposes.

Responsibilities

• Analyzing existing tools to identify state-of-the-art design concepts
• Learn DFT and iJTAG concepts
• Develop a complete Python tool that would wrap around existing tools or perform the full iJTAG operation itself
• Develop an FPGA prototype to experiment with the iJTAG tool
• Use open-source tools to create the test platform

Qualifications

• Are currently enrolled and studying towards a Masters Degree in Electronics, Embedded systems or Microelectronics. Candidates with alternative degrees will also be considered if they have relevant experience.
• Demonstrate autonomy and a strong willingness to learn new concepts.
• Have proficiency in C++, as the role involves evaluating an existing solution developed in this language.
• Are familiar with FPGA development.

Qualities that will help your application stand out

• Experience in Python and C++
• Multi-threaded programming
• Experience with language parsers
• FPGA development
• Curiosity about technology outside of the classroom – personal projects, hackathons, or internships

Additional Information

We encourage early applications as we review them on a first come/first served basis.

Arm Internships require you to be enrolled in a higher education degree.

French law requires students to complete an internship agreement (Convention de Stage). This is a tripartite agreement signed by the student, their home university and host organization, that facilitates an internship in France. It defines duration, missions, remuneration and benefits, insurance in the event of an accident, etc. It is preferable that Arm’s own template of the agreement is used. Successful applicants will be required to provide contact details of the appropriate university representatives in order to have the agreement signed.

In Return

Working on interesting new projects with leaders in the field is exciting, but we also know how important it is to receive support. Throughout your internship you can expect regular feedback and development opportunities, social activities to connect with peers, an end-of-internship celebration, plus the opportunity to be considered for future Graduate positions (subject to performance).

In addition to a competitive salary and rewards package, our on-the-job learning and mentoring/buddy schemes provide opportunities for learning and networking from the best in the industry.

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, while recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.