Optimization Of a Keccak Hardware Accelerator Protected Against Side-Channel Attacks H/F

CEA; Grenoble; Sur place; EUR 20 000 - 40 000; Plein temps

Résumé du poste

A leading research organization in Grenoble seeks an intern to optimize a Keccak hardware accelerator against side-channel attacks. This internship targets master's students with experience in FPGA and ASIC design, focusing on enhancing efficiency while maintaining security. Candidates should have skills in RTL modeling and synthesis tools. Join a team dedicated to cutting-edge research in the field of post-quantum cryptography.

Qualifications

• Graduate-level experience in FPGA and ASIC design required.
• Familiar with arithmetic circuit microarchitectures.
• Understanding of randomness generation mechanisms.

Responsabilités

• Optimize a masked Keccak accelerator for side-channel attack protection.
• Analyze area overhead introduced by masking and randomness.
• Model optimized design in HDL and synthesize on FPGA or ASIC.

Connaissances

FPGA design

ASIC design

RTL modelling (VHDL or Verilog/SystemVerilog)

Synthesis tools (Synopsys Design Compiler, Xilinx Vivado)

Formation

Master's degree in relevant field

Description du poste

Overview

Category: Electronics components and equipments

Contract: Internship

Job title: Optimization of a Keccak Hardware Accelerator Protected against Side-Channel Attacks H/F

Subject

With the advent of Post-Quantum Cryptography (PQC), new cryptographic standards rely heavily on complex mathematical operations that must remain secure even against quantum computers. However, their implementations are vulnerable to side-channel attacks, which exploit physical leakages such as power or electromagnetic emissions to recover secret information. Masking countermeasures mitigate these attacks by splitting sensitive data into random shares, ensuring that no single computation reveals useful information to an attacker.

The objective of this internship is to optimize a first-order masked Keccak accelerator implementing Domain Oriented Masking (DOM) for protection against side-channel attacks. The work focuses on reducing both the hardware area and the amount of randomness required by the countermeasure, without compromising security. Starting from the existing masked SHA-3 accelerator developed at CEA [1], the student will analyze the main sources of area overhead introduced by the masking and randomness generation mechanisms. Based on this analysis, alternative micro-architectural solutions for the non-linear Keccak steps and the randomness dispatcher will be investigated to improve efficiency. The optimized design will be modeled in HDL and synthesized on FPGA or ASIC targets to evaluate cost, performance, and scalability. Security validation will be conducted using Test Vector Leakage Assessment (TVLA). The expected outcome is a more compact and resource-efficient masked Keccak accelerator that maintains first-order resistance, enabling practical deployment of secure SHA-3 hardware in post-quantum cryptographic systems.

This offer is dedicated to master students looking for an ambitious research-oriented internship. If you are looking for an experience in ASIC and FPGA design with industrial-grade tools and processes, this internship is perfect for you! It is required to have graduate-level experience in FPGA and ASIC design and be familiar with arithmetic circuit microarchitectures, RTL modelling (VHDL or Verilog/SystemVerilog) and synthesis (Synopsys Design Compiler, Xilinx Vivado).

Site and Location

Site: Grenoble

Location: Grenoble

General information

Organisation

The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas:

• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.

Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners. The CEA is established in ten centers spread throughout France.

Reference

2025-37905

Additional context

The LIST institute is part of the CEA (French Alternative Energies and Atomic Energy Commission) Technology Research Division. CEA-LIST brings together nearly 1,000 scientists, engineers and technicians, expert in smart digital systems. This internship will take place in the Grenoble site of the CEA-List institute, in a research team focused on integrated circuits design for applications such as cybersecurity, Internet of Things, artificial intelligence, and emerging technologies.