[CONTRACT] UVM Verification Engineer

microTECH Global Ltd; À distance; EUR 55 000 - 75 000; Plein temps

Résumé du poste

A technology firm is seeking a UVM Verification Engineer for a 6-month contract based in France with the possibility of remote work. The ideal candidate will have a strong background in ASIC verification and is experienced in System Verilog and UVM. Responsibilities include joining a new team and contributing to new and existing ASIC projects. Knowledge of wireless communications such as WiFi or 5G is advantageous.

Qualifications

• Strong background in ASIC Verification.
• Proficient in System Verilog and UVM.
• Experience with IP block level verification.

Responsabilités

• Join a newly formed team within the client’s offices.
• Expand on projects being worked, both new and existing.
• Work on new and existing ASIC projects.

Connaissances

ASIC Verification

System Verilog

UVM

IP block level verification

Multi-clock domains

RTL in Verilog, VHDL

Complex ASIC/FPGA designs

Knowledge of WiFi or 5G

Description du poste

Job Description

Job Title : UVM Verification Engineer

Location : France / Remote

Duration : 6 months initial

Start Date : ASAP

A client based in France is looking for a UVM verification Engineer, this will be for an initial 6 month contract with extensions. The role can be performed remotely but any on-site would be welcomed.

The successful Verification engineer will be joining a team that is being newly formed within our client's offices and will help to expand on projects being worked, both new and existing within other teams. You will be involved in new and existing ASIC projects.

Skills :

• Strong background in ASIC Verification
• System Verilog / UVM
• Knowledge of IP block level verification
• Multi-clock domains
• RTL within Verilog, VHDL and / or SystemVerilog
• Used to working with complex ASIC and / or large FPGA designs
• Knowledge of wireless communications such as WiFi or 5G would be good