Senior Validation Engineer (Permanent)

Berkeley Square - Talent Specialists in IT & Engineering; Madrid; Presencial; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

A growing semiconductor company in Madrid seeks an experienced RTL Verification Engineer to lead verification for next-generation AI/ML compute platforms. The ideal candidate will have a Master’s or PhD in Electrical Engineering or Computer Science, and 5-8+ years of digital verification experience in SystemVerilog and UVM. Collaboration with design teams and strong problem-solving skills are essential. Scripting expertise in Python, Bash, and Tcl is required.

Formación

• Master’s or PhD in Electrical Engineering or Computer Science.
• 5 to 8+ years of experience in digital verification using SystemVerilog and UVM.
• Strong experience with scripting and simulation tools.
• Fluent in English (C1 level).
• Excellent problem-solving and collaboration skills.

Responsabilidades

• Lead RTL verification for AI/ML compute platforms.
• Develop and execute UVM-based testbenches for IP and SoCs.
• Apply formal and dynamic verification techniques.
• Conduct coverage analysis, regressions, and debugging.
• Collaborate with design and architecture teams.
• Automate verification workflows using Python, Bash, and Tcl.

Conocimientos

Digital verification

SystemVerilog

UVM

Scripting

Problem-solving

Educación

Master’s or PhD in Electrical Engineering or Computer Science

Herramientas

Python

Bash

Tcl

Descripción del empleo

About the Role

Join a fast‑growing European semiconductor company developing customizable high‑performance RISC‑V cores with vector / tensor acceleration and proprietary high‑bandwidth memory IP.

Key Responsibilities

• You’ll lead RTL verification for next‑gen AI / ML compute platforms.
• Develop and execute UVM‑based testbenches for complex IP and SoCs.
• Apply formal and dynamic verification techniques.
• Drive coverage analysis, regressions, and debug.
• Collaborate closely with design and architecture teams.
• Automate verification workflows (Python, Bash, Tcl).

Requirements

• Master’s or PhD in EE / CS.
• 5–8+ years in digital verification (SystemVerilog / UVM).
• Strong scripting and simulation tool experience.
• Fluent English (C1).
• Team player with excellent problem‑solving skills.

Nice to Have

• RISC‑V core or SoC verification experience.
• Knowledge of vector / tensor compute or memory architectures.