Senior Digital Design Engineer

Jordan martorell s.l.; Barcelona; Presencial; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

A technology company in Barcelona seeks a PCIe Lead / Senior Digital Design Engineer with a strong background in SoC/ASIC integration. The ideal candidate will lead the design of PCIe subsystems and drive efficient interactions within complex SoC environments. The role requires 4+ years of industrial experience in PCIe design and proficiency in RTL design. Join a dynamic team focused on high-performance solutions.

Formación

• 4+ years of industrial experience (Engineer) or 6+ years (Lead).
• Strong hands-on experience with PCIe design and/or integration.
• Solid background in SoC/ASIC IP integration.

Responsabilidades

• Own the architecture and lead the RTL implementation of PCIe subsystems.
• Drive efficient interaction between the PCIe block and CPU clusters.
• Integrate and verify IPs within large SoC environments.

Conocimientos

PCIe design and/or integration

SoC/ASIC IP integration

RTL design (Verilog or VHDL)

Basic block-level testing

Familiarity with one protocol (AXI, CHI, AHB)

Educación

Master’s degree or PhD

Herramientas

C++, Python, Perl, Bash, or TCL

Version control (git, svn)

Descripción del empleo

ROLE: PCIe Lead / Senior Digital Design Engineer

LOCATION: Barcelona, Spain

SALARY: Negotiable

DURATION: Permanent

We’re looking for an experienced engineer to take a leading role in the design and integration of PCIe solutions within complex SoC/ASIC environments. If you’re passionate about microprocessor architecture, high-speed I/O, and building high-performance subsystems, this role puts you at the centre of it.

What you’ll be doing:

• Own the architecture and lead the RTL implementation of PCIe subsystems
• Drive efficient interaction between the PCIe block and CPU clusters using AMBA-CHI coherency
• Integrate and verify IPs within large SoC environments
• Work closely with cross-functional teams of digital, verification, and architecture experts

What you’ll bring:

• 4+ years industrial experience (Engineer) or 6+ years (Lead)
• Strong hands-on experience with PCIe (design and/or integration)
• Solid background in SoC/ASIC IP integration
• Proficiency in RTL design (Verilog or VHDL)
• Experience with basic block-level testing
• Familiarity with at least one protocol: AXI, CHI, or AHB

Nice to have:

• Master’s degree or PhD
• Knowledge of C++, Python, Perl, Bash, or TCL
• Experience working with version control (git, svn)
• Understanding of coherency protocols
• Experience with CXL