Senior ASIC Digital Backend Physical Implementation Engineer

Ciena; Ottawa; On-site; CAD 109,000 - 174,000; Full time

Job summary

A leading technology company in Ottawa is looking for a Digital ASIC Physical Implementation Engineer. This role involves defining physical architecture, collaborating on design elements, and utilizing EDA tools for optimal performance. The ideal candidate must have a Bachelor’s degree in Electrical or Computer Engineering, experience in ASIC physical design, and proficiency with EDA tools like Genus and Innovus. The salary range is CAD 109,000 - 174,000, complemented by a robust benefits package.

Benefits

Medical, dental, and vision plans

401(K) with company matching

Employee Stock Purchase Program

Paid holidays and vacation time

Employee Assistance Program

Qualifications

• Knowledge in submicron technology nodes and ASIC backend flow.
• Experience with multiple power domains and knowledge of UPF and SOCV/POCV concepts.
• Ability to run Static Timing Analysis (STA) and debug timing issues.

Responsibilities

• Scope and define physical architecture of ASIC designs using EDA tools.
• Collaborate with RTL circuit designers to create optimal floorplans.
• Navigate EDA tool settings to ensure signoff-quality results.

Skills

ASIC physical digital design

Timing closure experience

Script development

EDA tool proficiency

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

Genus

Innovus

PrimeTime

Tempus

Redhawk

Voltus

Calibre

Job description

As the global leader in high‑speed connectivity, Ciena is committed to a people‑first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well‑being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute:

Ciena’s WaveLogic family of products is a cornerstone of our optical fiber transmission solutions, driving innovation and success in the telecommunications industry. As a Digital ASIC Physical Implementation Engineer, you will play a critical role in developing large mixed‑signal SoC ASICs targeting advanced technology nodes. Your contributions will directly impact the performance, power efficiency, and area optimization of our industry‑leading WaveLogic ASICs.

In this role, you will:

• Scope and define the physical architecture of designs, utilizing EDA vendor tools to build, adapt, and maintain a robust flow from netlist to full closure and GDSIIೃಹ generation.

• Partner with RTL circuit designers and otherhea lent engineers to create optimal floorplans, design power grids, and clock distribution networks that achieve the best performance and power efficiency.

• Navigate and fine‑tune EDA tool settings, parameters, and attributes to ensure signoff‑quality results with an optimal balance of performance, power, and area (PPA).

• Identify and propose alternative implementations, trade‑offs, and solutions to achieve lower power consumption and higher performance.

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• Collaborate with analog designers and ASIC/SoC teams to integrate analog blocks seamlessly into the overall design.

• Conduct initial Place & Route trials to refine design and correlation, influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable physical design.

• Generate and implement timing ECOs to achieve timing closure, as well as functional ECOs to address RTL feature fixes when necessary.

• <_categoria>Utilize tools like Formality or Conformal for formal verification, analyzing reports andDaveensuring design accuracy and integrity.

• Write scripts to enhance productivity and efficiency for yourself and other backend engineers. Collaborate with Mesmo and technology vendors to drive fixes, improve workflows, and evaluate new tools and features.

• Produce concise status reports at various stages of development, highlighting trade‑offs and providing actionable insights.

• Understand and implement Design for Test (DFT) requirements provided by the ASIC service provider. Use physical‑aware synthesis features to mitigate timing issues associated with layout and/or ECOs.

• Resolve timing challenges associated with DFT through scan chain reordering, placement, and CTS constraints.

• Run Static Timing Analysis (STA), analyze timing reports, and debug issues related to timing constraints, missing exceptions, and tool correlation between P&R and STA tools, ect.

• Your expertise in physical design, collaboration with cross‑functional teams, and ability to innovate will be instrumental in advancing Ciena’s cutting‑edge optical networking solutions.

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

The Must Haves:

• Minimum Bachelor’s degree in Electrical or Computer Engineering,411 computer science or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure.

• Understanding of the submicron technology nodes full backend ASIC flow and timing/power/area analysis and trade‑offs.

• Proven experience working with Genus, Innovus, and PrimeTime Imported.

• Practical experience developing scripts to automate tasks throughout the backend flow.

• Experience in working with multiple power domains and knowledge of UPF and SOCV/POCV concepts.

Assets:

• Experience with Tempus, Redhawk/Voltus, and Calibre.

Pay Range:

The annual salary range for this position is $109,000 - $174,000 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locationsรว reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non‑Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

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