RISC-V Processor Certification (RISC-V Mentorship)

Riscv; Remote; CAD 30,000 - 60,000; Part time

Job summary

A technology organization in Canada is offering a mentorship role focused on open-source RISC-V development and testing. The selected candidate will identify and analyze RISC-V cores, develop a unified database, and run tests to ensure functionality and usability. This position provides an excellent opportunity to learn essential software and hardware skills specific to RISC-V technology, including debugging, processor customization, and automation of testing processes.

Qualifications

• Strong understanding of open-source RISC-V development.
• Ability to develop and debug low-level drivers.
• Familiarity with test case compilation and execution.

Responsibilities

• Identify open-source cores to test and develop a UDB file for each.
• Implement core-specific macros and linker scripts.
• Run tests and report any issues or bugs found.

Skills

RISC-V development

Debugging

Software customization

Test automation

Job description

The RISC-V Certification Steering Committee is developing certification tests to prove that RISC-V processors conform to the ratified specifications. The goal of this mentorship project is to run the tests on as many open-source RISC-V cores as possible, and improve the usability of the tests, debug any issues found in the tests, and report any real bugs that might be found in the cores.

This work will involve:

• Identifying multiple open-source cores to test
• For each core:
  • Develop a Unified Database (UDB) file specifying the extensions and parameters supported by the core
  • Implement trick box macros to trigger interrupts, print characters to a console, and terminate a simulation in a core-specific manner
  • Create a linker script appropriate to the memory map of the core
  • Compile the tests with the core-specific trick box and linker scripts
  • Run the relevant tests on the core
• Identify and fix any problems in the tests that make them hard to run on a core
• Identify and fix any problems with the flow or documentation
• Identify and report any bugs found in the cores

The work will start with Phase 0 tests of the RVI20 profile with the RV{32/64}IMACDF extensions in machine mode. As time permits, it will continue to the Phase 1 MC100 microcontroller profile with machine mode, traps, Zicsr, and Zicntr, and then to the Phase 2 RVA23 application processor profile with all privilege modes, vector and hypervisor.

Repository URL: https://github.com/riscv-non-isa/riscv-arch-test/tree/cvw

Learning Objectives

In this mentorship, you will learn software and hardware skills for open-source RISC-V development and testing. You will learn to bring up an open-source processor, customize low-level trick box drivers to that processor, compile test cases, automate running them on the processor, report and debug issues, and share your results.

Coding Challenge

https://docs.google.com/document/d/1KA_fOmGA0Va-rE7QC7IQACydKZ-n7zmc/edit?usp=sharing&ouid=104823481179142905076&rtpof=true&sd=true