ASIC design and verification Engineer

Targeted Talent; Kitchener, Waterloo; On-site; CAD 80,000 - 100,000; Full time

Job summary

A leading technology recruitment agency is seeking an experienced hardware design engineer located in Kitchener, Canada. The ideal candidate will have more than 5 years in hardware systems design, particularly in FPGA/ASIC development, and will be familiar with Agile methodologies. Key responsibilities include designing hardware architectures and developing RTL modules. This role offers competitive benefits including 20 vacation days and unlimited sick days.

Benefits

20 vacation days

Strong health and extended health benefits

Unlimited sick days

Stock options

Qualifications

• 5+ years of experience in hardware systems design.
• Proficiency in RTL performance improvement.
• Experience with PCIe PHY and controller IP integration.

Responsibilities

• Design, analyze, and evaluate hardware architectures.
• Develop RTL modules in Verilog/SystemVerilog.
• Conduct hardware testing, debugging, and verification.

Skills

Communication Skills

Critical Thinking

Problem Solving

Education

B.S., M.S., or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Verilog/SystemVerilog

Python

FPGA/ASIC Development Tools

Job description

About the Company:
Our client is a company building the world's highest- performance pure digital AI inference chip. The ideal candidate will possess excellent communication skills, a creative mindset, strong critical thinking abilities, and the capability to analyze and resolve complex hardware-related issues.


Responsibilities:

• Design, analyze, and evaluate hardware architectures.
• Develop RTL modules in Verilog/SystemVerilog.
• Conduct hardware testing, debugging, and verification.
• Scripting and basic software development for hardware design support.
• Apply Agile methodologies, including code reviews and sprint planning.

Requirements:

• B.S., M.S., or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of experience in hardware systems design, focusing on RTL performance improvement and lab bringup.
• Proficiency in FPGA/ASIC development tools and RTL programming languages (Verilog/SystemVerilog preferred).
• Python coding skills (C, C++ are assets).
• Experience with PCIe PHY and controller IP integration and bringup.
• Extensive ASIC and FPGA programming experience, including timing closure and resource management.
• Familiarity with Agile methodologies.
• Technical leadership in small team environments.

Perks:

• 20 vacation days
• Strong health and extended health benefits
• Unlimited sick days
• Stock options

Please apply even if you don't check all the boxes. We are an inclusive and diverse company and welcome applicants from all backgrounds.