NPU Physical Design Engineer

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading technology company in Singapore seeks a candidate for a role focused on the physical design and development of advanced AI processors. This position emphasizes collaboration with teams in Taiwan and Singapore, and requires expertise in digital design processes including timing optimization and power management. Applicants should hold a degree in Electrical or Computer Engineering, with experience in high-speed processor implementations and relevant design tools. A commitment to communication and scripting is essential for success.

Qualifications

• Bachelor/Master’s Degree in Electrical/Computer Engineering is required.
• Experience with high-speed NPU/GPU/CPU Subsystem RTL integration is preferred.
• Good communication and scripting skills are essential.

Responsibilities

• Responsible for physical design and development of AI processors and DSP.
• Involve in synthesis, floor-planning, and power optimization.
• Collaborate with colleagues in Taiwan and Singapore.

Skills

High-speed NPU/GPU/CPU Subsystem RTL Integration

Good communication skills

Scripting skills

Education

Bachelor/Master’s Degree in Electrical/Computer Engineering

Tools

Synopsys ICC2/FC

Cadence Innovus

Redhawk

Voltus

PrimeTime

Tempus

Tweaker

PrimeClosure

Job description

Important Note:

This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.

Job Descriptions:

• Responsible for physical design and development activities of MediaTek Ghz, AI processors and neural network DSP
• Involve in activities encompass physical design and analysis of complex and timing- critical AI processors and neural network DSP Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing, power optimization and physical verification
• Work closely with MediaTek colleagues in Taiwan and Singapore in implementation methodology co-development and flow deployment

Requirements:

• Bachelor/Master’s Degree in Electrical/Computer Engineering
• High-speed NPU/GPU/CPU Subsystem RTL Integration experience or IP/Block/SoC Design experience is preferred
• Experience with Synopsys ICC2/FC (preferred) or Cadence Innovus tools from netlists to GDS
• Experience in high-speed processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification)
• Experience with power noise and reliability tools such as Redhawk and Voltus
• Experience with timing signoff tools such as PrimeTime and Tempus and timing closure tools such as Tweaker and PrimeClosure
• Knowledge of high-speed/low power IP and custom circuit design
• Good communication and scripting skills

EA License No. 01C4394 • RCB No. 200007268E

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