Staff Digital Design Engineer — Mixed-Signal IP Leader

Infineon Technologies AG; Padova; In loco; EUR 40.000 - 60.000; Tempo pieno

Descrizione del lavoro

A leading semiconductor company in Padova is seeking a Digital Design Engineer to design and develop mixed-signal IPs for ASICs. The role involves writing SystemVerilog code, collaborating with analog designers, and ensuring IP quality through rigorous verification. The ideal candidate should have a degree in Electrical Engineering and at least 3 years of experience in digital design. This position offers a dynamic work environment within a diverse team.

Servizi

Competitive salary

Dynamic work environment

Diversity and inclusion initiatives

Competenze

• At least 3 years of experience in digital design with focus on mixed-signal IPs.
• Proficiency in writing RTL code and testbenches.
• Strong understanding of digital design principles.

Mansioni

• Design, develop, and verify digital components of mixed-signal IPs for ASICs.
• Write and maintain SystemVerilog code for digital IP blocks.
• Collaborate with analog designers to ensure integration.

Conoscenze

Problem-solving skills

Collaboration skills

Attention to detail

Adaptability

Formazione

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering

Strumenti

System Verilog

Industry-standard design tools

Descrizione del lavoro

A leading semiconductor company in Padova is seeking a Digital Design Engineer to design and develop mixed-signal IPs for ASICs. The role involves writing SystemVerilog code, collaborating with analog designers, and ensuring IP quality through rigorous verification. The ideal candidate should have a degree in Electrical Engineering and at least 3 years of experience in digital design. This position offers a dynamic work environment within a diverse team.