Principal Analog Design Engineer

Corps Partners; Cascina Vignazza; In loco; EUR 85.000 - 110.000; Tempo pieno

Descrizione del lavoro

A leading engineering firm in Pavia, Italy is seeking a Principal Analog Design Engineer to join their Optical PHY team. The ideal candidate will have a Master's degree or Ph.D. in Electrical Engineering, along with 12-15 years of professional experience in analog design. This full-time position offers a competitive salary between €85,000 to €110,000 plus bonuses, and involves duties such as circuit design, verification, and project management. Fluency in Italian and English is preferred.

Servizi

Signing bonus

Paid relocation

Competenze

• 12-15 years of professional experience in related field.
• Experience in designing high-speed analog circuits.
• International team experience required.

Mansioni

• Analyze block specifications for transistor-level design.
• Validate and model circuit blocks.
• Collaborate with cross-functional teams.
• Manage tasks from simulation to high-volume production.

Conoscenze

IC design from architecture through lab characterization

Analog design

Custom analog layout supervision

Communication skills

Presentation skills

Documentation skills

Fluent in Italian

Fluent in English (minimum B2)

Formazione

Master’s degree or Ph.D. in Electrical Engineering or a related field

Strumenti

EDA CAD tools

Descrizione del lavoro

Overview

Principal Analog Design Engineer – Pavia, Italy

€85,000 to €110,000 + Bonus + SIGNING BONUS + Paid Relocation

This role is a key position within our Optical PHY (CE-OPHY) team, which is part of our Central Engineering division. Our team is at the forefront of designing high-speed and optical transceivers for modern communication infrastructure. This technology is critical for addressing the explosive demand for bandwidth in mega data centers that power social media, video-on-demand, gaming, and other real-time data streams. We are dedicated to developing innovative, first-to-market chips and subsystem solutions that push the boundaries of data rates and power efficiency.

Responsibilities

• Design & Architecture: Analyze and interpret block specifications, taking ownership of transistor-level design and selecting the most appropriate topologies. Design entire analog macros or IPs from initial concept to final mass production.
• Verification & Validation: Model and validate circuit blocks. Supervise and guide layout activities, provide guidelines, and conduct post-layout verifications to ensure design integrity.
• Collaboration & Leadership: Collaborate with other engineering teams to enhance solutions and participate in cross-functional meetings. Train and mentor junior designers to build the team's technical strength.
• Project Management: Manage pre-silicon tasks (simulation, modeling) and post-silicon tasks (lab characterization, debugging, correlating measurements to simulations) through to high-volume production.

Qualifications

• Education & Experience: Master’s degree or Ph.D. in Electrical Engineering or a related field; 12-15 years of professional experience.
• Technical Skills: Proven experience designing ICs from architecture through lab characterization and volume production. Solid experience in analog design, preferably in the multi-GHz range. Proficiency supervising custom analog layout, using standard EDA CAD tools, and debugging designs to correlate simulations with measurements.
• Preferred Qualifications: Experience with multi-Gbps electrical SerDes or electro-optical transceivers. Knowledge of advanced CMOS nodes, including FinFET, is advantageous.
• Personal Skills: Strong communication, presentation, and documentation skills. Proficiency in Italian and English (minimum B2) with international team experience.
• Work Model: On-site, full-time position located in Pavia, Italy.