PMU Verification Engineer - SystemVerilog/UVM Expert

Apple; Livorno; In loco; EUR 40.000 - 60.000; Tempo pieno

Descrizione del lavoro

A leading technology company in Livorno, Italy, is seeking a Verification Engineer to develop verification plans and maintain test environments. The ideal candidate will have a Master's in a related field, deep knowledge of SystemVerilog, and experience with scalable test-benches. Responsibilities include generating tests, debugging issues, and collaborating with engineering teams. This full-time position offers a chance to work in an innovative environment committed to inclusion and diversity.

Competenze

• Experience developing scalable and portable test-benches.
• Experience defining coverage space and analyzing results.
• Experience with Assertion Based Verification.

Mansioni

• Develop verification plans in coordination with design leads.
• Maintain verification test bench components and environments.
• Generate directed and constrained random tests.

Conoscenze

Fluency in English

Excellent communication skills

Deep knowledge of SystemVerilog

Experience with hardware description languages

Experience with Python, Perl, or TCL

Understanding of AI and ML

Formazione

Masters degree in Electrical Engineering, Embedded Systems, Computer Science, or related field

Descrizione del lavoro

A leading technology company in Livorno, Italy, is seeking a Verification Engineer to develop verification plans and maintain test environments. The ideal candidate will have a Master's in a related field, deep knowledge of SystemVerilog, and experience with scalable test-benches. Responsibilities include generating tests, debugging issues, and collaborating with engineering teams. This full-time position offers a chance to work in an innovative environment committed to inclusion and diversity.