Jobs in Manchester, United Kingdom
Mixed Signal Design Verification Engineer
Chipright
Functional Assessor Remote
Ingeus UK
Apprenticeship Funding Compliance Manager (Military)
Pearson Education
Interpreter Translator Required in Normanton
Translation Empire PK
Remote Technical Design Coordinator
Arco Recruitment Ltd
Remote Data Entry Clerk - Work at Home
TowardJobs
SuccessFactors product Owner CGEMJP
Experis
Connect with headhunters to apply for similar jobsBusiness Development Manager
Recruit 12
Strategic Sales Manager - UK | AI & Datacenter Solutions Sales London (Remote) Fully Remote
Submer - Datacenters That Make Sense
Freelance Social Media Content & Community Manager
DMCG Global
Employee Benefits Consultant
Mulberry Recruitment
Educational Psychologist - Remote - Lancaster - Sanctuary Personal
Sanctuary Personnel Ltd
Work at Home Data Entry Agent - Part Time
TowardJobs
Account Coordinator - United Kingdom (London) - Bilingual French and/or Spanish
Accommodations Plus International
Work at Home Data Entry Agent - Part Time
TowardJobs
Work From Home Customer Service Representative - Part Time
TowardJobs
Contracts Manager Remote
Gabbott Recruitment Online Limited
Part-Time Data Entry Clerk - Customer Service Agent
TowardJobs
Mobile HGV Technician
Euro Projects Recruitment
Sustainability Reporting Analyst
STARK Building Materials UK
Mixed Signal Design Verification Engineer
Job summary
A leading engineering firm in the UK is seeking a Mixed Signal Design Verification Engineer. The role involves implementing System Verilog models, performing verification tasks, and understanding AMS simulations. Experience with UVM environments is essential. This position offers a very attractive salary.
Qualifications
- Experience in implementing System Verilog Models for Analog blocks.
- Proficient in Model vs Schematic Verification.
- Understanding of UVM environment and Top Level Test cases.
Responsibilities
- Implement System Verilog Models for Analog blocks.
- Verify Models against Schematics with Test bench implementation.
- Run AMS simulations and regressions.
Skills
Salary: Very Attractive Rate
Location: N/A
Mixed Signal Design Verification Engineer
- Implementation of System Verilog Models for the Analog blocks
- Model vs Schematic Verification – System Verilog Test bench implementation including assertions
- Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
- Understanding of UVM environment and implementing the Top Level Test cases in the environment
- Running regressions using VManager
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.
job faster
Follow us
