Front-End Digital Verification Engineer (Functional Verification) - Spain

CIS Electronics Engineering; España; A distancia; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

A leading technology firm in Spain is seeking a highly skilled Front End Digital Verification Engineer for a permanent position. This role involves functional verification of next-generation SoC designs, focusing on RTL level validation across various protocols. Candidates should have a solid background in verification techniques and the ability to debug complex issues. The position offers full remote working conditions.

Formación

• Solid background in Front End (RTL-level) Functional Verification.
• Hands-on experience with SystemVerilog, UVM, and assertions (SVA).
• Proven ability to debug complex design/verification issues.

Responsabilidades

• Develop and execute functional verification plans for complex SoC subsystems.
• Build and maintain System Verilog/UVM testbenches.
• Collaborate with design teams for RTL sign-off.

Conocimientos

Functional Verification

SystemVerilog

UVM

Debugging

Protocol Verification

Descripción del empleo

Front End Digital Verification Engineer (Functional Verification)

We are seeking a highly skilled Front End Digital Verification Engineer to join our team and contribute to the development and validation of next-generation SoC designs. This role is focused on functional verification at the RTL level, ensuring design correctness and compliance across complex high-speed and low-speed interfaces.

This will be for a permanent employment opportunity with full remote working conditions based anywhere in Spain.

Key Responsibilities

• Develop and execute functional verification plans for complex SoC subsystems.
• Build and maintain System Verilog/UVM testbenches with protocol VIPs and assertions.
• Verify PCIe Gen7 interface with CXL (version TBD).
• Verify low-speed control/debug interfaces including SPI, JTAG, and SMBus.
• Validate integration of Embedded Microcontroller cores (ARC32 or RISC-V).
• Verify AXI-based system interconnects and bus protocols.
• Track functional and code coverage, driving verification closure.
• Collaborate closely with design and architecture teams to root-cause issues and ensure robust RTL sign-off.

Required Skills & Experience

• Solid background in Front End (RTL-level) Functional Verification.
• Hands-on experience with SystemVerilog, UVM, assertions (SVA), and coverage-driven verification.
• Familiarity with protocol verification IP (VIP) for PCIe, CXL, AXI, or equivalent.
• Strong knowledge of high-speed and low-speed interface protocols.
• Experience verifying Embedded processors or microcontrollers (RISC-V, ARC, or similar).
• Proven ability to debug complex design/verification issues.

Nice to Have

• Experience with performance verification and system-level test scenarios.
• Knowledge of verification acceleration/emulation flows.
• Familiarity with formal verification techniques.