Senior Pre-Silicon Verification Engineer

Intel; Toronto; On-site; CAD 153,000 - 218,000; Full time

Job summary

A leading semiconductor company in Toronto is looking for a Senior Pre-Silicon Verification Engineer specializing in mixed-signal verification. This role involves developing verification strategies, conducting functional verification, and collaborating with design teams to ensure designs meet performance and power standards. Ideal candidates should have a Bachelor's in Electrical Engineering and 5+ years experience in verification, with skills in UVM/SystemVerilog. Competitive salary based on experience, with on-site work requirements.

Benefits

Competitive salary

Comprehensive benefits package

Professional development opportunities

Qualifications

• 5+ years of experience in digital design verification or mixed-signal verification.
• 3+ years of experience with pre-silicon verification environment architecture and development.
• Experience with complex mixed-signal IP verification or system-level verification.

Responsibilities

• Perform functional verification of mixed-signal logic components.
• Develop comprehensive IP verification plans and scalable environments.
• Execute verification plans and debug complex issues in the pre-silicon environment.

Skills

Digital design verification

Mixed-signal verification

Scripting (Python preferred)

Education

Bachelor's degree in Electrical Engineering or related field

Tools

UVM/SystemVerilog

Job description

Job Details

Intel's Central Engineering Group is seeking a Senior Pre‑Silicon Verification Engineer specializing in mixed‑signal verification to ensure complex analog and digital designs meet specification requirements before fabrication. This role focuses on developing comprehensive verification strategies for digital and mixed‑signal IP blocks, creating advanced behavioral models, and executing thorough verification plans that validate functional, performance, and power requirements across Intel's cutting‑edge semiconductor designs.

Key Responsibilities

Mixed‑Signal Verification & Modeling

• Perform functional verification of digital and mixed‑signal logic components including analog behavioral modeling and advanced verification techniques (UVM, real‑number modeling, AMS simulation).
• Create verification environments that accurately model analog‑digital interactions and validate designs across process, voltage, and temperature (PVT) variations.

Verification Planning & Environment Development

• Develop comprehensive IP verification plans, test benches, and scalable verification environments for mixed‑signal microarchitecture specifications.
• Build verification frameworks supporting regression testing, continuous integration, and both digital and analog verification flows.

System Simulation & Debug

• Execute verification plans, analyze power/timing/performance metrics, and conduct system‑level simulations and corner‑case analysis.
• Replicate, root‑cause, and debug complex issues in the pre‑silicon environment, implementing corrective measures to resolve failing tests.

Cross‑Functional Collaboration & Process Improvement

• Collaborate with digital and analog architects, RTL developers, and physical design teams to meet functional, performance, and power goals.
• Document test plans, drive technical reviews, and maintain/improve verification infrastructure and methodology while ensuring smooth pre‑silicon to post‑silicon correlation.

Qualifications

The minimum qualifications listed below would be obtained through a combination of industry‑relevant job experience, internship experience, and/or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related field of study.
• 5+ years of experience in digital design verification or mixed‑signal verification.
• 3+ years of experience with pre‑silicon verification environment architecture and development.
• Experience with complex mixed‑signal IP verification or system‑level verification.
• Experience in both digital verification methodologies (UVM/SystemVerilog).
• Perl, HTML, Python or similar scripting (Python preferred).

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a STEM related field of study.
• Experience with working in mixed‑signal design like SerDes or PLLs.
• Experience with SerDes PHY verification.
• Experience driving verification methodology changes and initiatives.
• Experience with Mixed Signal Verification (MSV).
• Experience with Gate Level Simulation (GLS).
• Experience with concepts of DFT, ATE, HVM.

What We Offer

• Competitive salary and comprehensive benefits package.
• Opportunity to work on Intel's most advanced mixed‑signal designs and technologies.
• Access to cutting‑edge mixed‑signal verification tools and simulation infrastructure.
• Collaboration with world‑class analog and digital design engineers and architects.
• Professional development opportunities in advanced mixed‑signal verification techniques.
• Direct impact on Intel's leadership in mixed‑signal semiconductor innovation.

Salary

Annual Salary Range for jobs which could be performed in Canada: CAD 153,910.00–217,280.00
Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.

Canada Accommodation

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.