Senior ASIC Verification Engineer: FEC & SystemVerilog

Ciena; Ottawa; On-site; CAD 152,000 - 244,000; Full time

Job summary

A leading technology company in Ottawa is seeking a Senior Digital Verification Engineer to enhance their Wavelogic modem family. This role focuses on validating functions for Forward Error Correction (FEC) systems using advanced verification strategies in a collaborative environment. The ideal candidate has a Bachelor's degree in Electrical or Computer Engineering and significant experience in C/C++ and System Verilog. Competitive compensation and various benefits are offered.

Benefits

Medical, dental, and vision plans

401(K) with company matching

Employee Stock Purchase Program (ESPP)

Paid vacation and sick leave

Discretionary incentive bonus

Qualifications

• Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators.
• Proven ability to determine digital verification and coverage strategies.

Responsibilities

• Implement innovative verification strategies to validate FEC IP.
• Collaborate with engineers and architects to simulate functional blocks.
• Create testbench environments and components using System Verilog UVM.

Skills

C/C++

System Verilog

UVM

Forward Error Correction (FEC)

Problem-solving

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Jira

GIT

Job description

A leading technology company in Ottawa is seeking a Senior Digital Verification Engineer to enhance their Wavelogic modem family. This role focuses on validating functions for Forward Error Correction (FEC) systems using advanced verification strategies in a collaborative environment. The ideal candidate has a Bachelor's degree in Electrical or Computer Engineering and significant experience in C/C++ and System Verilog. Competitive compensation and various benefits are offered.