Staff Engineer DFT

Ambiq Micro, Inc.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

A leading semiconductor provider in Singapore seeks a DFT Engineer to develop and implement low-power design for test (DFT) architectures. The ideal candidate will have a BS/MS in Electrical Engineering and at least 10 years of experience in DFT implementation. Responsibilities include scan insertion and boundary scan development using EDA tools. Strong communication skills and experience in RTL are essential. Candidates should value innovation and collaboration, contributing to transformative solutions in energy efficiency.

Qualifications

• At least 10 years of experience in DFT implementation.
• Skilled in different types of DFT structures, including scan and MBIST.
• Strong verbal and written English communication skills.

Responsibilities

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC.
• Develop and implement low-power DFT architecture and infrastructure.
• Generate structural test vectors and improve coverage, test time, and test cost.

Skills

DFT implementation

Low-Power DFT

Boundary scan

Timing concepts

Tcl scripting

RTL experience

Communication skills

Education

BS/MS in ECE/EE

Tools

EDA tools

GlS (gate level simulation)

Job description

Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub- and near-threshold technologies. With the increasing power requirements of artificial intelligence (AI) computing, our customers are relying on our solutions to deliver AI to edge environments. Our hardware and software innovations fundamentally deliver a multi-fold improvement in power consumption over traditional semiconductor designs without expensive process geometry scaling. We began in 2010 by addressing the power consumption challenges of battery-powered devices at the edge, where they were most pronounced . As of the beginning of 2025, we ' ve shipped more than 2 8 0 + million units worldwide.

Our innovative and fast-moving teams of design, research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin ), Taiwan (Hsinchu), China ( Shanghai and Shenzhen), and Singapore. We value relentless technology innovation, a deep commitment to customer success, collaborative problem-solving, and an enthusiastic pursuit of energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies . We encourage and nurture an environment that fosters growth and opportunities to work on complex, meaningful, and challenging projects, creating a lasting impact and shaping the future of technology. Join us on our quest for enabling billions of intelligent devices. The intelligence everywhere revolution starts here.

Responsibilities

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
• Develop and implement low-power DFT architecture and infrastructure.
• Generate structural test vectors, analyse, and improve coverage, test time and test cost.
• Perform pre/post-layout scan and MBIST simulations.
• Work with designers on STA, physical, power and logical issues related to DFT.
• Work with test engineers to bring up test vectors on silicon.

Qualifications

• BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.
• Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
• Experience in creating and implementing hierarchical DFT architecture in complex SoC.
• Experience in Low-Power DFT and MBIST.
• Experience in test time and test coverage analysis for scan and MBIST patterns.
• Experience in working with test engineering team to bring up production test program.
• Extensive knowledge of timing concepts and constraint development.
• Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
• Experience in RTL is required.
• Experience in scripting like Tcl is preferred.
• Experience with GLS (gate level simulation) is preferred.
• Motivated, self-driven engineer with attention to detail.
• Strong verbal and written English communication skills.

What You Need

We're seeking passionate technologists who thrive on pushing boundaries, solving complex challenges, and driving transformative solutions.

At Ambiq , you'll collaborate with a dynamic team that values relentless innovation, customer-centric thinking, and continuous learning. If you're a self-motivated, creative problem-solver eager to push technological limits and make a meaningful impact in energy efficiency, this is your opportunity to grow, excel, and turn groundbreaking ideas into reality.

Most importantly, the successful candidate will be able to live the Ambiq Shared Values:

• Innovate: We tenaciously find ways to break down the barriers to possible solutions
• Collaborate: We proactively communicate and encourage each other to be better.
• Focus: We keep the voice of the customer at the center of everything we do.
• Learn: We strive for continuous improvement and are always curious.
• Achieve: We execute on quality and follow through on our commitments.

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