Senior Engineer, Design Verification

AMBIQ MICRO SINGAPORE PRIVATE LTD.; Singapore; On-site; SGD 80,000 - 100,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking a Verification Engineer to verify digital and mixed-signal designs for IoT applications. Ideal candidates will possess a BSEE/MSEE degree and have 5-8 years of experience in verification. Responsibilities include developing test plans, executing SoC-based verification, and automating testing environments. The role emphasizes energy-efficient solutions and a strong understanding of low-power design. Join us in shaping the future of intelligent devices.

Qualifications

• 5-8 years of experience in block, sub-system, and full-chip verification.
• Experience with ARM processor-based designs and low-power design techniques is a plus.
• C-based verification in an SoC environment is required.

Responsibilities

• Verify digital and mixed-signal designs for IoT applications.
• Develop test plans at block, sub-system, and chip level.
• Automate the test environment for randomized testing.

Skills

Digital and mixed-signal design verification

C-based lib packages

SystemVerilog and UVM

Arm processor-based designs

Python

Education

BSEE/MSEE Degree

Job description

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days) while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 230 million units as of October 2023. For more information, visit www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

Responsibilities

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Specific responsibilities include:

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
• Develop test plans at block, sub-system, and chip level.
• Execute SoC-based verification at full-chip.
• Write C-based lib packages and tests.
• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
• Automating the test environment for randomized testing and scoreboarding.
• Utilize advanced debugging techniques to identify and resolve design and verification issues.
• Perform root-cause analysis and work with design teams to fix identified issues
• Define and track functional and code coverage metrics to ensure thorough verification.
• Ensure that verification quality meets or exceeds industry standards and project requirements.
• Edge-based AI inference is preferred.

Requirements

What you need to have to be successful

• BSEE /MSEE Degree with 5 - 8 years of experience in block, sub-system, and full-chip verification
• Should have delivered multiple chips functioning to Specification.
• Identify and manage verification deliverables, milestones, and schedules.
• Proactively identify potential verification risks and develop mitigation strategies.
• Collaborate with design, architecture, and software teams to understand and verify design intent.
• Communicate verification progress, issues, and results to stakeholders and management.
• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges
• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
• C-based verification in an SoC environment is required
• Experience with ARM processor-based designs and low-power design techniques is a plus.
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
• Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5
• Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power