Memory Layout Engineer | Cadence & Verification Pro

Broadcom Inc.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking an experienced engineer with strong expertise in memory layout design and verification tools. The role involves applying complex layout guidelines and leading projects effectively. Candidates should have a minimum of 2 to 3 years of experience, proficiency in Cadence layout tools, and a strong background in physical verifications. Ideal applicants will demonstrate leadership skills and be self-reliant in managing tasks.

Qualifications

• Minimum of 2 to 3 years of experience in layout design.
• Strong experience in memory layout design and physical verifications.
• Ability to work independently and lead a team.

Responsibilities

• Understand and apply necessary layout guidelines and process rules.
• Complete quality layout and verification within the planned schedule.
• Lead or train junior engineers and manage projects.

Skills

Cadence layout

Cadence schematic capture

CALIBRE & Hercules verification tools

Strong layout knowledge in submicron process

Digital layout experience

Analog layout experience

Memory layout design experience

Physical verifications (LVS, DRC, ERC, Antenna, Electro Migration)

Scripting and SKILL Programming

Leadership and project management

Tools

Cadence Layout tools VIRTUOSO

CALIBRE verification tools

Job description

A leading semiconductor company in Singapore is seeking an experienced engineer with strong expertise in memory layout design and verification tools. The role involves applying complex layout guidelines and leading projects effectively. Candidates should have a minimum of 2 to 3 years of experience, proficiency in Cadence layout tools, and a strong background in physical verifications. Ideal applicants will demonstrate leadership skills and be self-reliant in managing tasks.