Digital IC Design Engineer

ESPRESSIF SYSTEMS (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 40,000 - 70,000; Full time

Job summary

A pioneering technology company in Singapore is seeking a Digital IC Design Engineer (SoC) to join the team. This role involves developing next-generation AI chips and collaborating closely with verification, front-end, and software teams. Ideal for junior engineers, the opportunity allows for hands-on experience in advanced SoC design projects. Candidates should have a Bachelor's degree in Electrical Engineering and 1 to 5 years of experience in digital IC design.

Qualifications

• 1 to 5 years of relevant experience in digital IC/ASIC design.
• Familiarity with ASIC design flow.
• Awareness of low-power design methodologies.

Responsibilities

• Contribute to RTL design of SoC modules and assist in IP core integration.
• Support chip-level system design tasks.
• Collaborate with verification and testing teams.

Skills

Understanding of digital circuit fundamentals

Proficiency in Verilog HDL

Good problem-solving skills

Strong communication skills

Education

Bachelor’s degree in Electrical Engineering

Tools

EDA tools (e.g., Synopsys, Cadence)

Job description

We are looking for a talented Digital IC Design Engineer (SoC) to join our growing team in Singapore. In this role, you will be involved to develop the next-generation AI chips based on a revolutionary architecture. You will work closely with verification, front-end, and software teams to deliver high-quality digital IC solutions. This is an excellent opportunity for junior engineers to develop their skills and gain hands-on experience in advanced SoC design projects.

Key Responsibilities

• Contribute to RTL design of SoC modules and assist in IP core integration.
• Support chip-level system design tasks, including clock/reset architecture, low-power design techniques, and bus architecture.
• Collaborate with verification and testing teams to perform module-level and system-level validation.
• Assist front-end engineers in netlist delivery and help resolve timing issues.
• Provide support for driver development, debugging, and technical documentation.

Requirements

• Bachelor’s degree or higher in Electrical Engineering (or equivalent).
• 1 to 5 years of relevant experience in digital IC/ASIC design.
• Strong understanding of digital circuit fundamentals and proficiency in Verilog HDL.
• Familiarity with ASIC design flow and EDA tools (e.g., Synopsys, Cadence).
• Basic understanding of CPU and Cache architectures, instruction set architectures (ISA), and compiler principles.
• Knowledge of bus systems, DMA, and peripheral interface design.
• Awareness of low-power design methodologies.

Preferred Qualifications

• Internship or project experience in SoC or ASIC design.
• Familiarity with standard bus protocols (e.g., AMBA, AXI, AHB, APB).
• Exposure to synthesis, timing analysis, or DFT concepts.
• Good problem-solving skills and eagerness to learn in a collaborative environment.
• Strong communication skills and ability to document technical work clearly.