Verification Engineer

Chipright; United Kingdom; On-site; GBP 40,000 - 60,000; Part time

Job summary

A leading technology verification company in the United Kingdom seeks a contractor for verification environments of RTL designs. The candidate should have extensive experience in using hardware verification languages like SystemVerilog or Specman, and must be familiar with UVM methodologies. Understanding end-to-end verification processes and familiarity with tools like Mentor Questasim is essential. Competitive compensation is offered.

Qualifications

• Extensive experience in designing verification environments for complex RTL designs.
• Well-versed in using SystemVerilog or Specman language.
• Must have detailed knowledge of verification methodologies like UVM.

Responsibilities

• Work on UVM based verification of a complex multi-unit System IP product.

Skills

Designing and implementing verification environments

Class based hardware verification languages

Verification methodologies such as UVM

End-to-end verification processes

Constrained random stimulus understanding

Familiarity with Mentor Questasim

Familiarity with GIT

Tools

Synopsys VCS

Cadence Incisive

Job description

Experience Required

• Extensive experience of designing and implementing verification environments for complex RTL designs.
• Well-versed in the use of class based hardware verification languages e.g. SystemVerilog or Specman ‘e.’
• Detail Knowledge of Verification methodologies such as UVM.
• In-Depth understanding of end-to-end verification processes, from test plan creation through to verification closure.
• Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioural functional models.
• Ability to quickly understand and apply complex specification detail.
• Familiarity with Mentor Questasim simulator required.
• Synopsys VCS & Cadence Incisive nice to have.
• The system that would be worked by the contractor would be able to run on these simulators.
• Familiarity with GIT.
• Scope of the project: UVM based verification of a complex multi unit System IP product.