Senior IP Design Engineer

Stackstudio Digital Ltd.; Bolton; Hybrid; GBP 60,000 - 80,000; Full time

Job summary

A leading technology firm in the UK is seeking a Senior IP Design Engineer for a hybrid role involving work in Cambridge, London, or Milton Keynes. The successful candidate will design, implement, and optimize IP for AMD Adaptive SoCs, collaborating with cross-functional teams. Required skills include deep experience with SystemVerilog HDL and knowledge of high-speed protocols like 100Gb Ethernet and PCIe Gen5. This role requires a strong understanding of FPGA/Adaptive SoC development flows, making it ideal for someone with relevant expertise.

Qualifications

• Deep hands-on experience with SystemVerilog HDL for RTL design.
• Proven ability to develop IP targeting FPGA / Adaptive SoC platforms.
• Strong experience with high-speed connectivity protocols.

Responsibilities

• Develop RTL in SystemVerilog for high-performance designs.
• Collaborate with teams on integration, timing closure, and validation.
• Support CI/CD development workflows using Git and automation.

Skills

SystemVerilog HDL

100Gb Ethernet

PCIe Gen5

AMBA / AXI protocols

Job description

Job Title: Senior IP Design Engineer

Location: Cambridge OR London OR Milton Keynes (Hybrid- 1-2 Days) Duration: Fixed term contract

Job Overview: Scope of Work

The selected engineer will work closely with internal architecture, RTL, verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs. Responsibilities include:

• Developing RTL in SystemVerilog for high-performance FPGA / Adaptive SoC designs
• Implementing and optimizing high-speed connectivity protocols
• Collaborating with cross-functional teams on integration, timing closure, and validation
• Driving improvements across synthesis, place and route, and timing flows
• Supporting CI / CD development workflows using Git and scripting automation

Required Skills & Experience

The proposed candidate must meet the following qualifications:

• A. RTL Design & Coding
  • Deep hands‑on experience with SystemVerilog HDL for RTL design
  • Proven ability to develop IP targeting FPGA / Adaptive SoC platforms
• B. High-Speed Protocols
  • Strong experience with
  • 100Gb Ethernet
  • PCIe Gen5
  • AMBA / AXI interface protocols
• C. Adaptive SoC / FPGA Expertise
  • In-depth understanding of FPGA / Adaptive SoC development flows, in...