Senior Design Verification Engineer

Queen Square Recruitment; Remote; GBP 80,000 - 100,000; Full time

Job summary

A leading global technology organization is looking for an experienced Senior Verification Engineer to support verification for high-speed networking. This fully remote contract role involves developing UVM-based verification environments and collaborating with design and firmware teams. Candidates should have strong experience with constrained-random verification and familiarity with 100Gb Ethernet or PCIe Gen5. This is a 6-month contract with high potential for extension, offering exciting opportunities in a fast-paced environment.

Benefits

Fully remote contract flexibility

Long-term programme with extension potential

Technically challenging work

Qualifications

• Strong hands‑on experience with UVM and constrained-random verification.
• Proven background in test planning and coverage closure.
• Experience with 100Gb Ethernet and/or PCIe Gen5.

Responsibilities

• Develop and execute UVM-based verification environments.
• Perform constrained-random verification and coverage-driven sign‑off.
• Integrate and validate VIP for high-speed networking protocols.

Skills

UVM and constrained-random verification

Test planning and coverage closure

100Gb Ethernet or PCIe Gen5

AMBA / AXI protocols

Python scripting for verification

CI/CD regression flows

Git proficiency

Adaptive SoC design flows

Embedded processor co-simulation

Job description

senior Verification Engineer – High-Speed Networking (Contract, Remote – UK)

A leading global technology organisation is seeking an experienced Senior Verification Engineer to support the verification of high-speed networking IP on a remote contract basis.

This is a 6-month contract with strong potential for extension, offering the opportunity to work on cutting‑edge SoC and connectivity technologies in a fast‑paced engineering environment.

The Role

You will be responsible for verifying high-speed connectivity IP using advanced verification methodologies and class‑based UVM environments. The role includes coverage closure, VIP integration, and supporting complex SoC‑level verification activities.

Key Responsibilities

• Develop and execute UVM-based verification environments
• Perform constrained-random verification and coverage-driven sign‑off
• Integrate and validate VIP for high-speed networking protocols
• Support CI/CD-based regression workflows
• Collaborate with design, firmware, and system teams on SoC debug

Essential Skills & Experience

• Strong hands‑on experience with UVM and constrained-random verification
• Proven background in test planning and coverage closure
• Experience with 100Gb Ethernet and / or PCIe Gen5
• Knowledge of AMBA / AXI protocols
• Python scripting for verification and automation
• Experience with CI/CD regression flows
• Proficiency with Git
• Exposure to Adaptive SoC design flows (e.g. Vivado / Vitis)
• Understanding of embedded processor co-simulation and SoC debug

Contract Details

• Location : Remote (UK-based)
• Contract Length : 6 months (extension likely)
• Engagement : Contract
• Rate : Market competitive

Why Apply?

• Work on next‑generation high‑speed networking technologies
• Fully remote contract flexibility
• Long‑term programme with extension potential
• Technically challenging and rewarding verification work