Analog Designers with Image Sensor Experience

Chipright; United Kingdom; Remote; GBP 40,000 - 70,000; Full time

Job summary

A technology firm in the UK is seeking an Analog Design Engineer with image sensor experience to join their team. The ideal candidate will hold a Bachelor Degree in Electronics, have 4-8 years of experience in Analog Design, and possess proficiency in Cadence tools. Key tasks include design and verification of various analog blocks, porting processes, and conducting schematic simulations. This role offers an attractive salary and the opportunity to work collaboratively in a team environment.

Qualifications

• Minimum 4-8 years of industry experience in Analog Design.
• Previous experience working on image sensors and related components.
• Familiarity with 65nm CMOS technology.

Responsibilities

• Design and verification of various blocks in analog design.
• Porting of 65nm CMOS process to another technology.
• Conduct schematic design and simulation.

Skills

Analog Design

Image Sensor

Communication Skills

Education

Bachelor Degree in Electronics

Tools

Cadence toolsuite

Verilog

Job description

Analog Designers with Image Sensor Experience

Salary: Very attractive rate

Location: N/A

We are seeking Analog Design Engineers with Image Sensor Experience who meet the following requirements:

• Must hold a Bachelor Degree in Electronics or equivalent.
• Minimum 4-8 years industry experience in Analog Design.
• Previous experience working on image sensors, pixel arrays, ADC's, DAC's, bandgap references, amplifiers, charge pumps would be preferable.
• Previous work on memory blocks would be an added advantage.
• Previous exposure working on 65nm cmos or similar is essential.
• Familiarity with Cadence toolsuite.
• Any previous Verilog experience would be beneficial.

The successful candidate will have proficient communication skills and the ability to work closely with other designers as part of a team.

Key tasks include:

• Design & verification of various blocks listed above.
• Porting of 65nm cmos process to another.
• Schematic design & simulation.
• May need to provide system model support where a block spec is changed.