Lead SoC Verification Architect (Hybrid)

SiPearl; Massy; Hybride; EUR 70 000 - 90 000; Plein temps

Résumé du poste

A leading microprocessor firm in France is seeking a Verification Architect to lead the design of verification platforms for next-gen SoCs. The ideal candidate will have extensive experience in ASIC/SoC verification and proficiency in SystemVerilog, C, and Python. Responsibilities include defining architecture, developing test environments, and mentoring engineers. The role supports both on-site and hybrid working models.

Prestations

Annual bonus

Meal vouchers

Health insurance

Mental health support

Training and personal development

Qualifications

• Minimum 7–10 years of experience in ASIC / SoC verification.
• 3–5 years as an architect or lead.
• Proficiency in SystemVerilog / UVM, VHDL / Verilog.

Responsabilités

• Define the verification platform architecture.
• Develop and maintain test environments and simulations.
• Lead and mentor a team of verification engineers.

Connaissances

SystemVerilog / UVM

ASIC/SoC verification

Leadership

C / C++

Python / TCL scripting

Communication protocols

Fluent French

Professional English

Formation

Master’s degree or PhD in electronics/microelectronics

Outils

Synopsys VCS

Cadence Xcelium

Mentor Questa

Description du poste

A leading microprocessor firm in France is seeking a Verification Architect to lead the design of verification platforms for next-gen SoCs. The ideal candidate will have extensive experience in ASIC/SoC verification and proficiency in SystemVerilog, C, and Python. Responsibilities include defining architecture, developing test environments, and mentoring engineers. The role supports both on-site and hybrid working models.