Senior DSP & Digital Communications Design Engineer (9 months contract) - Remote EU [25151]

CS GROUP; A distancia; EUR 50.000 - 80.000; Jornada completa

Descripción de la vacante

A leading aerospace solutions provider in Tres Cantos, Spain, is seeking a skilled engineer with a background in telecommunications and a passion for developing algorithms for quantum key distribution tailored for satellite communication. The role requires over 7 years of experience in creating communication architectures, debugging FPGA and microprocessor solutions, and utilizing tools like MATLAB and Simulink. Candidates should possess strong signal processing skills and be motivated to learn new technologies in the space business.

Formación

• 7+ years of experience in designing and developing SDR/digital communication algorithms.
• Experience in debugging FW-FPGA and C-microprocessor solutions during HW-FW integration.
• Knowledge of System on Chip devices like MPSoC and RFSoC.

Responsabilidades

• Design and develop algorithms for quantum key distribution tailored for satellite communication.
• Utilize Model-Based Design principles with MathWorks tools.
• Implement and test algorithms in a Hardware-in-the-Loop environment.

Conocimientos

Signal processing

Digital communications

Model-based design

Quantum Key Distribution (QKD)

FPGA programming

C/C++ programming

Python programming

Educación

Telecommunication Engineer (MSc)

Herramientas

MATLAB

Simulink

HDL Coder

Spectrum Analysers

Network Analysers

Signal Analyzers

Logic Analysers

Oscilloscopes

BER meters

Descripción del empleo

You will be working integrated in a multidisciplinary team together with System, ground and satellite equipment’s, VHDL, SW and HW engineers.

You will perform the following tasks:

• Design and develop algorithms for quantum key distribution (QKD) tailored for satellite communication.
• Utilize Model-Based Design principles, specifically leveraging MathWorks tools such as Simulink and MATLAB for system modeling and simulation.
• Implement and test the algorithms in a Hardware-in-the-Loop (HIL) environment to validate their performance under realistic conditions.
• Work closely with VHDL & SW engineers to ensure seamless implementation of the algorithms on FPGA/Microprocessor/SoC platforms for satellite hardware.
• Document all development processes, methodologies, and results to ensure compliance with project standards and facilitate knowledge transfer within the team.""

Qualifications

• Telecommunication Engineer (MSc), or equivalent, with firm background on Signal processing, digital communications and protocols. Model based design, model based system engineering and cryptography/security protocols are very valued.
• More than 7 years-experience in designing and development of SDR/digital communication architectures and algorithms applied to communication systems: modulation schemes, error correction coding, characterisation of communication links (channel distortion, EVM, BER, FER).
• More than 7 years of Experience in designing of Signal Processing Algorithms (DSP), specification and performances evaluation oriented to FPGAs or Microprocessors. A deep understanding of floating-point to fixed-point algorithm translation is a must.
• More than 7 years of Experience in debugging the FW- FPGA solution or C-Microprocessors solution at laboratory during HW-FW integration.
• Knowledge of FPGA, microprocessors and System on Chip devices (MPSoC, RFSoC)
• Use of test instrumentation: Spectrum Analysers, Network Analysers, Signal Analyzers, Logic Analyzers, Data Patterns Generators, Oscilloscopes, BER meters
• Knowledge of Simulation software: MATLAB, Simulink, HDL Coder.
• Knowledge of Software Programming: C/C++, Python.

Team work, improvement spirit, pragmatic, results oriented, dynamic, accountable and proactive.

Capable of having a solution’s overall vision and to focus on each individual component.

Motivated to learn new technologies, and space-business processes and tools

Capable to solve engineering problems within risk, cost & schedule constraints and Valued Experience in Agile methodology.