Senior Digital Design Engineer - (Visa Sponsorship Supported)

European Tech Recruit; Köln; Vor Ort; EUR 55.000 - 75.000; Vollzeit

Zusammenfassung

A leading semiconductor company in Cologne is seeking a skilled Digital Design Engineer. This role involves owning RTL design and micro-architecture for digital subsystems, developing backend flows, and integrating digital with analog subsystems. Candidates should have strong skills in RTL design and experience with EDA tools. This position offers a chance to work on innovative technology for advanced wireless infrastructure.

Qualifikationen

• 3-5 years of relevant experience for Mid-Level, 6+ years for Senior-Level.
• Experience in digital IC design essential.
• Strong problem-solving skills and attention to detail required.

Aufgaben

• Own RTL design and micro-architecture of digital subsystems.
• Develop backend flow, including synthesis and timing closure.
• Support integration of digital blocks with analog subsystems.

Kenntnisse

RTL design using SystemVerilog / VHDL

Logic synthesis

Static timing analysis

Scripting (Python, Tcl)

Low-power design techniques

Mixed-signal integration

Ausbildung

MSc or PhD in Electrical Engineering or related field

Tools

EDA tools from Cadence, Synopsys, or Mentor

Jobbeschreibung

Overview

Digital Design Engineer

A fantastic opportunity for an experienced Digital Design Engineer to join an award-winning semiconductor company whose main product is a break-through and patented wide band width transceiver “microchip for application in e.g. ultrafast 5G-A and 6G wireless infrastructure equipment and devices.

Responsibilities

• Own RTL design and micro-architecture of digital subsystems (e.g., DSP blocks, control logic, interfaces).
• Develop and optimize backend flow, including synthesis, floorplanning, placement and routing (P&R), timing closure, and signoff (STA, LVS, DRC).
• Perform logic synthesis and work with physical design teams to ensure a clean handoff and alignment across digital and mixed-signal boundaries.
• Support integration of digital blocks with analog / mixed-signal subsystems.
• Generate documentation, testbenches, and support post-silicon bring-up and debugging.

Your Profile

• Strong proficiency in RTL design using SystemVerilog / VHDL, digital verification, and scripting (Python, Tcl, etc.).
• Experience with EDA tools from Cadence, Synopsys or Mentor for logic synthesis, static timing analysis, and backend implementation.
• Familiarity with low-power design techniques, clock domain crossing (CDC), and hierarchical SoC design.
• Hands-on experience in physical implementation (floorplanning, P&R, CTS, STA, DRC, LVS).
• Experience with modern process nodes, especially 22FDX, 16 / 12nm FinFET, or similar. Good understanding of mixed-signal integration, top-level assembly, and testability concepts (DFT is a plus).
• Strong problem-solving skills, attention to detail, and ability to work independently.

Qualifications

• Mid-Level : 3–5 years of relevant experience in digital IC design.
• Senior-Level : 6+ years, with ownership of IP / SoC blocks or backend flows.
• MSc or PhD in Electrical Engineering, Microelectronics, or related field

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