Digital ASIC/FPGA Designer

Cynet systems Inc; Ottawa; On-site; CAD 100,000 - 130,000; Full time

Job summary

A technology solutions company is seeking an experienced Digital ASIC/FPGA Designer in Ottawa. The role requires deep expertise in ASIC RTL Design with a minimum of 15 years of experience and proficiency in Verilog/SystemVerilog. Candidates should also be familiar with networking standards like Ethernet and scripting languages such as Python, Perl, and TCL. This position offers the opportunity to work with advanced tools and methodologies in a dynamic environment.

Qualifications

• At least 15 years of experience in ASIC/FPGA design.
• Strong skills in RTL ASIC/FPGA design with Verilog and System Verilog.
• Knowledge of networking standards and wired communications protocols, such as Ethernet.

Responsibilities

• Perform ASIC RTL Design for various projects.
• Conduct Clock Domain Crossing (CDC) Analysis and debug functional simulations.
• Handle RTL synthesis and utilize front-end ASIC design EDA flows.

Skills

ASIC RTL Design

Verilog / SystemVerilog

Clock Domain Crossing (CDC) Analysis

Functional simulation debug

RTL Synthesis

Python

Perl

TCL

Education

Bachelor's degree in engineering or computer science

Tools

Client Design/Fusion Compiler

Client VCS simulation

MBIST

DFT

Vivado Design Suite

Job description

Job Description:

• ASIC RTL Design.
• Verilog / SystemVerilog.
• Clock Domain Crossing (CDC) Analysis.
• Functional simulation debug.
• RTL Synthesis.
• Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer science
• Experience in front-end ASIC design EDA flows including: Client Design/Fusion Compiler, Client VCS simulation; MBIST, DFT; CDC Lint tools.
• Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog.
• Knowledge of networking standards and wired communications protocols (such as Ethernet).
• Experience with scripting languages such as Python, Perl and TCL.
• Experience with client Vivado Design Suite.