Design Verification Manager

Riscv; Vancouver; Hybrid; CAD 100,000 - 130,000; Full time

Job summary

A leading technology firm is seeking a Design Verification Manager in Vancouver, BC. This hybrid role involves leading a VLSI team and mentoring others while defining verification methodologies for next-gen RISC-V CPUs. The ideal candidate will have a background in engineering, experience with verification processes, and strong communication skills. This position allows for both onsite collaboration and remote work, enhancing the work-life balance of the team.

Qualifications

• Proven track record for verifying designs to tape out quality.
• Strong mastery of Unix and experience with scripting languages.
• Experience in CPU architecture, multi-core coherence, and FPU.

Responsibilities

• Mentor and teach verification approaches to team members.
• Track project schedules and provide status updates.
• Analyze CPU architecture and microarchitecture.

Skills

Team leadership

Communication

Verification methods

Problem analysis

Education

Bachelor’s or Master’s degree in related engineering field

Tools

Verilog

System Verilog

UVM

Unix

Scripting languages (make, shell, python)

Job description

Design Verification Manager

Vancouver, BC, Canada – Hybrid – onsite 25%-30% of the time and work from home.

Senior engineer or Junior Manager – experience with team leading required

Corporate Introduction

As a founding premier member of RISC-V International, Andes is the leading supplier and technological innovator in the RISC-V market with a wide range of processor products fulfilling performance/area/power requirements. Andes has perfected the technology of quick and efficient design of custom extensions to its proprietary CPU. With over 10 billion cumulative shipments of SoCs embedded with Andes CPU IP, Andes products have covered audio, Bluetooth, gaming, GPS, machine learning, MCU and more. Our design innovation enables us to quickly adapt to the rapidly evolving demands of RISC-V customers.

Founded in 2005, Andes yearly revenue has tripled in size from $10 million in 2017 to $30 million in 2021. Andes was ranked among “100 Fastest-Growing Companies” in 2020 by CommonWealth Magazine. Headquartered in Taiwan, Andes is capitalizing on its current growth by branching out its offices to the US and Canada to expand on its current 300 employee workforce. Employees are valued as the key ingredient to the success of the company. They will have an opportunity to create a strong and positive impact on the company, where feedback is encouraged and implemented.

Role

This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.

As a leader of this team, you will define verification methodologies, analyze problems, and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. You will have the opportunity to mentor junior members of the team. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.

Daily activity includes:

• Mentor/teach other verification members in their approaches
• Track schedule and project status
• Communication with team members to discuss technical details
• Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
• Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
• Hands-on verification work including verification regression management, debugging and bug-reports
• Technical documentation

Technical Requirements

• Bachelor’s or Master’s degree in related engineering field
• Proven track record for verifying designs to tape out quality
• Strong communication and leadership skills
• Experience using Verilog, System Verilog, UVM, coverage analysis, formal
• Strong mastery using Unix and scripting languages such as make, shell, perl or python
• Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)

Desirable Skills

• Experience coding in assembly languages
• Strong desire to learn and willing to devote extra effort to achieve perfection
• Strong team player and possess a positive attitude
• Multi-lingual
• Cross-site or multi-time zone experience
• Good time management skills