Design Engineer AI SoC Development

Intel; Remote; CAD 153,000 - 218,000; Full time

Job summary

A leading technology company is seeking an engineer for their AI SoC organization in Vancouver. This role focuses on RTL design, implementation, and validation for cutting-edge AI products. The ideal candidate will have strong experience in Verilog/SystemVerilog, synthesis tools, and must possess a Bachelor's degree in a relevant engineering field. The position offers a competitive salary and the flexibility of remote work. Join us to innovate in the field of AI hardware.

Qualifications

• Minimum 5+ years of experience in RTL design and implementation for ASIC/SoC development.
• Experience with synthesis tools and timing closure methodologies is crucial.
• Understanding of power optimization techniques is preferred.

Responsibilities

• Develop RTL in Verilog/SystemVerilog based on defined micro-architecture.
• Collaborate with verification teams to ensure robust validation.
• Support silicon bring-up and post-silicon validation activities.

Skills

RTL design and implementation

Verilog/SystemVerilog proficiency

Synthesis tools and timing closure

Clock domain crossings

Basic scripting skills (Python, TCL)

Education

Bachelor's degree in Electrical Engineering

Computer Engineering

Computer Science

Tools

EDA tools: HDL simulators

Static timing analysis tools

Formal verification tools

Job description

Job Details

Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.

Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.

Responsibilities

• Contribute to evaluation of architectural trade‑offs considering features, performance, and system constraints.
• Implement RTL in Verilog/SystemVerilog based on defined micro‑architecture; integrate IP blocks at top level and ensure synthesis‑ and timing‑clean design.
• Work closely with verification teams to achieve full coverage and robust validation.
• Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks.
• Support silicon bring‑up and post‑silicon validation activities, including debug and performance analysis.
• Collaborate with senior engineers to adopt best practices and improve design methodologies.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 5+ years of experience in/with:
  • RTL design and implementation for ASIC/SoC development
  • Proficiency in Verilog/SystemVerilog for RTL coding and design
  • Experience with synthesis tools and timing closure methodologies

Preferred Qualifications

• Understanding of clock domain crossings, power optimization, and timing closure
• Exposure to SoC system integration and CPU subsystem design
• Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
• Knowledge of high‑speed and low‑power design techniques
• Experience with static timing analysis (STA) tools and methodologies
• Hands‑on experience with formal verification tools and techniques
• Basic scripting skills (Python, TCL, etc.) for automation
• Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools

Job Type

Experienced Hire Shift: Shift 1 (Canada) Primary Location: Virtual Canada Additional Locations:

Business Group

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners.

Equal Employment Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Salary

Annual Salary Range for jobs which could be performed in Canada: CAD 153,910.00-217,280.00. Salary range dependent on a number of factors including location and experience.

Work Model

This role is available as a fully home‑based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. Job posting details (such as work model, location or time type) are subject to change.

Accommodations

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.