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Senior Staff Product Development Engineer

ADVANCED MICRO DEVICES (SINGAPORE) PTE LTD

Singapore

On-site

SGD 70,000 - 100,000

Full time

Today
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Job summary

A leading semiconductor company in Singapore is looking for a (Senior) MTS Product Development Engineer. This role is crucial for developing ATE test solutions to achieve NPI business goals. Applicants should have strong leadership, analytical skills, and expertise in DFT architecture. Responsibilities include driving test solution development, collaborating with various engineering teams, and optimizing testing processes for high performance computing environments. Experience in the semiconductor industry and ATE platforms is required.

Qualifications

  • Deep expertise in DFT architecture for SoC products.
  • Experience in test development, silicon characterization, and debugging.
  • Hands-on experience with ATE test development is preferred.

Responsibilities

  • Drive ATE test solutions to meet NPI business milestones and KPI.
  • Collaborate with cross-functional teams to ensure test quality.
  • Optimize manufacturing processes and test coverage.

Skills

Leadership
Problem-solving
Data analysis
Communication skills
Software programming
Testing expertise

Education

Degree in Engineering or related field

Tools

Advantest V93K
C++
Python
Linux
Job description
THE ROLE

We are the high-end test engineering team providing test solutions for Data Center Graphics (DCG) New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, enterprise servers, and Artificial Intelligence clusters.

If you are looking for a fulfilling and challenging career as an engineer leading NPI ATE Product Development, you are in the right place! As a (Senior) MTS Product Development Engineer, you will be responsible for developing and driving ATE test solutions to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership through interaction with design teams, Product & Test Engineering teams, Quality & Reliability teams, software & platform teams to come up with the best solution that balances quality and cost. You will experience working with and learning from AMD’s talented engineering teams around the world.

THE PERSON

We are seeking a technically strong, analytical, and resourceful individual with proven leadership and problem-solving capabilities. The ideal candidate will have deep expertise in DFT (Design-For-Test) architecture for SoC products, along with hands‑on experience in test development, silicon characterization, and debug—particularly in areas such as CReST, Functional/AVFS, and Thermal‑TSEN—across various industry-standard ATE platforms.

KEY RESPONSIBILITIES
  • Pre-silicon: Understand product features in depth, define test plans and requirements, and develop the necessary software and hardware infrastructure. Collaborate with Design and Platform Engineering teams to provide feedback that enhances future testability and design robustness.
  • Post-silicon: Deliver comprehensive test coverage and execute characterization plans on schedule. Responsibilities include debugging test performance issues, addressing yield and device marginalities, and optimizing manufacturing processes. Work closely with cross-functional teams to identify root causes through debug, characterization, and margin analysis.
  • Accountable to drive test solution/coverage development, optimization to meet business milestone, cost and quality in Functional/CReST (Cache Resident Self‑Test)/AVFS (Adaptive Voltage Frequency Scaling).
  • Functional-CReST/AVFS/Thermal ATE Test patterns & test flows/method development, debug, test and characterization
  • Pre-Silicon engagement with Design, test solution/methodology scoping, planning & validation
  • Post Silicon Bring up of test patterns leading to optimization for mass production enablement
  • Characterization execution/analysis and debug of Functional-CReST/AVFS/Thermal test/fails (including the RMA) in the new silicon designs and process technologies
  • Optimization of test coverage and flows for increased quality, yield, cost improvement, and test time reduction
  • Conduct engineering evaluations and analysis to drive closure of production issuesSolves complex, novel, and non-recurring problems; initiate significant changes to existing processes/methods and leads development and implementation
  • Influences technical decisions that have a significant impact on final product
  • Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
  • May provide technical supervision or mentoring junior engineers
PREFERRED EXPERIENCE
  • Experience in the semiconductor industry; candidates with a strong track record and less experience are also encouraged to apply.
  • Proven expertise in developing high‑quality test solutions from NPI through full-scale production.
  • Strong communication and presentation skills, with proficiency in data analysis and visualization.
  • Hands‑on experience with ATE test development and execution—preferably on Advantest V93K (SMT8 experience is a plus).
  • Familiarity with IP development and debugging is beneficial.
  • Working knowledge of functional test domains such as CReST (Cache Resident Self‑Test), AVFS (Adaptive Voltage Frequency Scaling), and Thermal TSEN calibration.
  • Solid understanding of power management features, calibration techniques, and active thermal control strategies.
  • Experience in power and performance characterization on ATE platforms.
  • Skilled in software programming and scripting (C++, Java, Groovy, Perl, Ruby, Python).
  • Proficient in both Windows and Linux operating systems.
  • Exposure to high-volume manufacturing (HVM) and data center infrastructure is a strong advantage.
  • Strong interpersonal, organizational, and analytical capabilities, with the ability to collaborate across geographically distributed teams.
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