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A significant technology firm in Singapore is seeking an experienced IC Design Engineer with a Master's or Bachelor's degree in Electrical/Electronics Engineering. The ideal candidate will have a strong background in design synthesis and timing closure, particularly with Synopsys and Cadence toolsets. Responsibilities include creating timing constraints and conducting logic equivalence checks. Candidates must possess excellent communication skills and the ability to excel both independently and as part of a team.
Next to Bendemeer MRT
Interested candidates may submit detailed CV with the following info: