Senior Library Characterization Engineer

Bitdeer Technologies Group; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading technology company in Bitcoin mining is seeking an experienced engineer to lead ASIC design. Responsibilities include standard cell design, backend design execution, and digital verification. Candidates should have a degree in Electrical Engineering and over 4 years of ASIC experience. The ideal candidate is proficient in tools like Siliconsmart and Innovus, with strong skills in Python automation. This role offers a dynamic environment and opportunities for growth in a fast-paced industry.

Benefits

Attractive welfare benefits

Training and mentoring opportunities

Qualifications

• 4+ years of experience in ASIC flow from design to tape-out on multiple chip projects.
• Expert-level knowledge of tools relevant to digital implementation and verification.
• Strong understanding of digital physical design flow from RTL to GDSII.

Responsibilities

• Lead full-flow generation and validation of customized libraries.
• Execute Chip Backend Design process utilizing relevant tools.
• Contribute to functional validation, including FPGA-based verification.

Skills

Standard Cell Performance Optimization

Chip Backend Design Process

Automation with Python/Tcl/Shell

FPGA-based Verification

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Siliconsmart

Hspice

Innovus

Vivado/ISE

Job description

About Bitdeer

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

What you will be responsible for

1. Standard Cell Design & Characterization Leadership

• Lead the full-flow generation and validation of customized characterization libraries (Liberty, noise, power) for advanced technologies.
• Characterize and optimize standard cell performance, focusing on key PPA metrics (timing, power, area, and stability) across multiple PVT corners.
• Utilize industry-standard tools like Siliconsmart and Hspice for transistor-level simulation, model extraction, and quality assurance.
• Develop and enhance automated Python/Tcl/Shell scripting flows for efficient library characterization and signoff.

2. Digital Implementation and Backend Signoff

• Execute and manage the Chip Backend Design process (Place & Route, Clock Tree Synthesis, Routing) utilizing tools like Innovus.
• Perform full signoff closure, including Static Timing Analysis (STA), power integrity checks, and Physical Verification (PV).
• Implement and analyze chip power data and sensor data extraction to validate Power, Performance, and Area (PPA) goals post-layout.
• Contribute to successful tape-outs on projects utilizing advanced nodes.

3. Design Verification and Methodology Integration

• Contribute to functional validation, including FPGA-based verification platforms (Vivado/ISE) and sophisticated simulation methods like XA simulation.
• Develop and maintain verification environments and scripts using Hardware Description Languages (Verilog/SystemVerilog).
• Translate characterization and PPA analysis data into improved library usage guidelines and implementation methodologies.

How you will stand out

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of direct project experience in the full ASIC flow from design through tape-out on multiple chip projects
• Demonstrated experience with advanced process nodes (7nm and below)
• Expert-level knowledge of tools including Siliconsmart, Hspice, Virtuoso, Innovus, and Vivado/ISE.
• Proficient in automation using Python, Tcl, and Shell.
• Extensive experience in standard cell library characterization, modeling, and flow development.
• Strong understanding of the complete digital physical design flow, from RTL to GDSII backend signoff.
• Familiarity with FPGA verification and digital

What you will experience working with us

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and an exciting start-up spirit;
• A fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.