Senior Engineer Yield Enhancement

Vanguard International Semiconductor Singapore Pte. Ltd.; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

A leading semiconductor company in Singapore is looking for an experienced individual to drive yield performance analysis and defect reduction activities. Responsible for supervising operations 24/7, training engineers, and ensuring wafer quality. Candidates should have a relevant degree and 2-8 years of experience in high volume manufacturing. Excellent communication skills and leadership capabilities are essential for this role.

Qualifications

• 2-8 years of relevant fab work experience in high volume manufacturing of electronics components preferred.
• Accountable for complying with EHSS policies and maintaining a safe workplace.
• Excellent leadership capability required.

Responsibilities

• Supervise YE Associate Engineers and ensure smooth inline shift operation.
• Train and certify YE Associate Engineers on recipe creation.
• Maintain internal SOP/OCAP and involve in audits.
• Track inline defect performance on a weekly basis.
• Provide scan support in low yield investigation.

Skills

Yield performance analysis

Defect reduction

Recipe creation

Defect characterization

Communication skills

Interpersonal skills

Education

Masters or Bachelor Degree in Electrical / Electronics / Chemical / Material Science Engineering

Tools

FIB

SEM

EDX

Brightfield

Darkfield

Job description

Job Purpose

• To liaise with module engineers on yield performance analysis
• To drive for defect reduction and yield improvement activities

Job Description

• Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation
• Train and certify YE Associate Engineers on recipe creation and defect source knowledge
• Maintain and enhance internal SOP/OCAP and involve in internal;/external audit
• Operate FIB/SEM/EDX for inline failure analysis
• Operate and create recipes in Brightfield, Darkfield and other defect inspection tools
• Perform partition analysis on defect source and detailed reports on issues
• Build and develop defect source land tool’s defect source fingerprinting
• Track inline defect performance by layer/process tool/chamber on weekly basis
• Perform killer ration analysis
• Perform defect characterization by process toolsContinuous improvement activities on defect reductions with Modules / vendors / equipment team
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities
• Provide scan support in low yield investigation & co-work with PI/PE on technology & device specific yield enhancement activities
• Automate daily activities to improve troubleshooting speed of team
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems

Job Requirements

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Material Science Engineering
• 2-8 years of relevant fab work experience in high volume manufacturing of electronics components in an MNC or semi-conductor industry preferred
• Responsible and accountable for complying with and implementing environmental, health, safety and security (EHSS) system, policies, procedures and guidelines that are applicable to your scope of work , thereby maintaining a healthy and safe workplace.
• Excellent interpersonal and communication skills with good leadership capability
• Team player