Senior Analog Mixed-Signal IC Layout Engineer

Astera Labs; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

Astera Labs is seeking a Senior Analog Mixed-Signal IC Layout Engineer to design advanced node CMOS products. Candidates should have at least 2 years of experience in high-speed analog IC layout development and a relevant engineering degree. This role focuses on layout creation and optimizing design parameters to minimize parasitic and skew.

Qualifications

• Minimum 2 years of experience in high-speed analog IC layout development in finFET technology.
• Experience with layout extraction and quality analysis for high-speed circuits.

Responsibilities

• Design advanced node CMOS products including floor planning and integrating layout.
• Collaborate with layout and design engineers across multiple time zones.

Skills

Layout extraction tools

SKILL scripting

TCL scripting

EMIR and antenna DRC rules

Education

Bachelor or advanced Diploma in Electrical Engineering

Job description

Senior Analog Mixed-Signal IC Layout Engineer

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications atwww.asteralabs.com .

Job Description:

As an AnalogMixed-Signal IC Layout Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include floor planning, creating layout of building blocks and integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, antenna rule on top of DRC and LVS. The company seeks a highly motivated and team orientated individual to work with both layout and design engineers across multiple time zone.

Basic Qualifications:

Bachelor or advanced Diploma degree in EE

Required Experience:

2+ years of experience developing layout for highspeed analog IC designs in finFET technology

Experience with layout extraction tools and to analyze layout parasitic to achieve high quality layout for highspeed circuits

EMIR and antenna DRC rules aware layout practices

Experience writing SKILL and TCL scripts is highlyrecommended

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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