Memory Design Automation – Memory modeling Engineer

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 80,000 - 100,000; Full time

Job summary

A leading technology firm in Singapore is looking for candidates to develop automation code and integrate it into memory compilers for ASIC design flow. This role involves executing EDA tools to ensure model correctness and collaborating with various engineering teams on memory design issues. Candidates should have a Bachelor’s degree in Electrical Engineering and a strong understanding of Verilog and EDA tools. This position is for future openings and not for immediate hiring.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related.
• Experience in Linux systems is a plus.
• Good understanding of Verilog syntax: behavioral, RTL, and synthesizable.

Responsibilities

• Develop automation code for memory compilers.
• Execute EDA tools for model verification.
• Collaborate with design teams to resolve model issues.

Skills

Verilog syntax understanding

Liberty timing syntax understanding

Scripting skills in Perl or Python

Experience with EDA tools

Education

Bachelor’s degree in Electrical Engineering

Tools

Linux systems

EDA simulation tools (VCS, NC)

DFT tools (Logicvision, Tessent, Fastscan)

Synthesis tools (Design compiler, Genus)

STA tools (PrimeTime)

Job description

Important Note: This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.

About the team

The MediaTek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness.

Job description

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.

Requirements

• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related.
• Experience in Linux systems will be a plus.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required.
• Experience with EDA tools will be helpful:
  • DFT: Logicvision, Tessent, Fastscan
  • Synthesis: Design compiler, Genus
  • Simulation tools: VCS, QuestaSim, NC
  • STA tools such as PrimeTime
• Good scripting and flow automation skills, in Perl or Python.