Layout Engineer

Broadcom Inc.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking an experienced engineer with strong expertise in memory layout design and verification tools. The role involves applying complex layout guidelines and leading projects effectively. Candidates should have a minimum of 2 to 3 years of experience, proficiency in Cadence layout tools, and a strong background in physical verifications. Ideal applicants will demonstrate leadership skills and be self-reliant in managing tasks.

Qualifications

• Minimum of 2 to 3 years of experience in layout design.
• Strong experience in memory layout design and physical verifications.
• Ability to work independently and lead a team.

Responsibilities

• Understand and apply necessary layout guidelines and process rules.
• Complete quality layout and verification within the planned schedule.
• Lead or train junior engineers and manage projects.

Skills

Cadence layout

Cadence schematic capture

CALIBRE & Hercules verification tools

Strong layout knowledge in submicron process

Digital layout experience

Analog layout experience

Memory layout design experience

Physical verifications (LVS, DRC, ERC, Antenna, Electro Migration)

Scripting and SKILL Programming

Leadership and project management

Tools

Cadence Layout tools VIRTUOSO

CALIBRE verification tools

Job description

Qualifications

• Strong layout knowledge with a minimum of 2 to 3 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm, 2nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem)

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.