Layout Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading technology firm based in Singapore is seeking an experienced engineer to manage and execute quality layout designs. Candidates should have a Bachelor's degree in Electronics Engineering with at least 2 years of layout experience. Familiarity with Cadence tools, good understanding of layout design in advanced processes, and strong communication skills are essential. Join a dynamic team to enhance innovative methodologies and maintain quality standards in layout design.

Qualifications

• Minimum 2 years of layout experience in electronics engineering.
• Experience in standard cells or full custom and analog layout design.
• Good understanding of Latch-up and ESD in CMOS process.

Responsibilities

• Understand and apply layout guidelines for quality layout.
• Complete quality layout and verification within planned schedule.
• Communicate well with the library team and share new ideas.

Skills

Electronics engineering

Layout design

Cadence Layout tools

Script Programming

Education

Bachelor's degree in Electronics Engineering

Tools

Cadence Virtuoso

Calibre verification tools

Job description

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O), new process rules and other technical requirements for quality layout.

• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set / Requirements:

• Bachelor Electronics engineering graduates with minimum 2 years of layout experience.
• Experience in standard cells or full custom and/or analog layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration (EMIR) in Finfet, CMOS process.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools.
• Good understanding of Latch-up and ESD in CMOS process and implementation for IO layout design.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Self-reliant, with ability to work independently as well as a team.
• Strong layout knowledge in advance process, e.g. 5nm, 3nm, 2nm